ADV7626 Rx termination problem(DC level gone)

Hi ,

I assume you have followed all the suggestions provided in the mentioned thread.

Could you please share your system’s register values during the issue scenario?

Thanks,
Ebin

Thank you for your reply.
Regarding the register values, as I am responsible for the hardware, I am not fully aware of the details, but I will look into it.
Based on what we have discovered during our current investigations, the PC is able to display the screen if, after switching channels, we perform a system power-down on the TX side before raising the HOTPLG, reset the hdcp_rept_edid_reset register (Tx main map 0x5a), and then raise the HOTPLG. The issue is that we are currently unsure of the correct sequence for such system power-down, HOTPLG and reset operations, or whether there are any other appropriate register operations required.

Hi,

1. We need the register values during the issue case for Analysis

2. Please follow the below sequence
a. Disable HPD
b. Enable TMDS termination
c. Wait 100 ms
d. Assert HPD
e. Read EDID
f. Wait for TMDS clock lock

3. Please refer HDMI Layout Guideline 

Thanks ,
Ebin

Thank you for the information.

We have carried out the sequence you described.
It appears that the main cause lies with the ADV7626 chip itself.
In particular, this chip has a defect relating to HDCP (depending on how it is used).
When an extender or HDMI device is connected to the RX or TX side (as seen in the logs),
switching the channel on the RX side—given that there is only one HDCP register in the block diagram—requires particular care regarding the handling of Akey-related matters if the source is an HDCP-encrypted source. Depending on the PC,
some may attempt to read the HDCP register before the PC’s HDMI DDC, which can result in HDCP authentication failing.
I have added processing steps within the sequence you provided.

a0. Channel switching
a. Disable HPD
b. Enable TMDS termination
c. Wait 100 ms
c1. Reset the hdcp_rept_edid_reset register after detecting 5V
d. Assert HPD
e. Read EDID
f. Wait for TMDS clock lock

In addition to the above steps, we have applied conditions to the HPD on/off state depending on the situation.

We have found that this can cause issues, at least in standard switching sequences.

Translated with DeepL.com (free version)

1663.ADV7625_Documentation_.zip7103.ADV7625-26-27_Ver1.0.txt.zip

Hi ,

I have attached the ADV752x User Manual and the script file for your reference. Kindly review these documents and try to validate the setup after disabling the HDCP option.

Thanks,

Ebin