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TMDS level shifter output stage (CML?) and IBIS modeling guidance

Category: Hardware

Hello,

I am working on a TMDS interface design using a level shifter such as MAX9406.

I am currently performing signal integrity (SI) analysis (eye diagram, jitter, amplitude behavior) using HyperLynx, but I could not find an IBIS model for this type of device.

I would like to understand the output stage behavior for accurate modeling.

Could you please provide guidance on:

  • Output stage type (CML, LVDS, or other)
  • Typical output current vs voltage characteristics
  • Whether the output behaves as a current-mode driver with external pull-up dependency
  • Recommended equivalent modeling approach for SI tools

This information is critical for accurate SI analysis in our design.

Thank you.

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