ADV7280A: Unstable chroma on first active line of BT.656 (STANAG Class C / NTSC)

jon510 on Mar 30, 2026
Category: Hardware
Hello,
I am using the ADV7280A with a STANAG 3350 Class C (NTSC RS-170A timing equivalent) composite input and 8-bit embedded BT.656-4 output.
Symptom:
The first active row of one field shows blinking colored dots (unstable chroma) on saturated colors such as SMPTE bars. Luma appears stable. Row 1 and the following rows are clean.
Isolation:
We checked the raw BT.656 output directly with an FPGA Integrated Logic Analyzer (ILA). The ADV7280A outputs 487 active lines, and the chroma variation is already present on the first active line of the raw byte stream before our FPGA crops it to 720x486 lines for the downstream modules.
Attempted fixes:
We tested several documented registers and EngineerZone-recommended initialization sequences, including 0x27, 0x2B to 0x2E, 0x3D, 0x38 to 0x39, and 0xEB to 0xEC, without any change to the first-line behavior. We have also checked with different video sources.
For reference, our baseline ADV7280A configuration is:
0x00 = 0x00
0x02 = 0x14
0x03 = 0x0C
0x04 = 0xBD
0x1D = 0x64
0x0F = 0x00
0x3A = 0x07
Questions:
1. Is this a known ADV7280A behavior for STANAG Class C / non-broadcast NTSC sources, specifically on the first active line of a field?
2. Could this be related to NTSC field-boundary / SCH burst phase behavior, or to how the ADV7280A handles chroma decoding / comb filtering on the first active line?
3. Is there any documented or undocumented register sequence that can improve first-line chroma stability, or is the recommended approach simply to mask this line downstream?
Thanks in advance for the support.
Kind regards,
Jonathan
Parents
Ebin
on May 15, 2026 6:21 AM
Fullscreen ADV7280A_CUST-VER.5.0.txt Download
;;DecoderLegacySupport = True;;
;;Reset = False;;
;;ReadInterface = True;;

##ASettings##
:Customer Version 5.0 August 2017 ADV7280A :
End

##01_Free-run Mode##

:Free-run, 480i 60Hz YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Free-run, Color Bars 480p YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write 
42 81 51 ; ADI Required Write 
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:Free-run, 576i 50Hz YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 84 ; Force standard to PAL
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Free-run, Color Bars 576p YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 84 ; Force standard to PAL
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write 
42 81 51 ; ADI Required Write 
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##02_CVBS AUTODETECT##

:Autodetect CVBS Single Ended In Ain 1, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Autodetect CVBS Single Ended In Ain 2, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Autodetect CVBS Single Ended In Ain 3, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Autodetect CVBS Single Ended In Ain 4, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##03_CVBS INTERLACED TO PROGRESSIVE##

:I2P - NTSC In Ain1,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain1, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - NTSC In Ain2,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain2, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - NTSC In Ain3,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain3, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - NTSC In Ain4,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain4, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##04_CVBS FAST Switch##

:FAST Switch CVBS Single Ended In Ain1, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:FAST Switch CVBS Single Ended In Ain2, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:FAST Switch CVBS Single Ended In Ain3, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:FAST Switch CVBS Single Ended In Ain4, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##05_CVBS FAST Switch I2P##

:I2P FAST SWITCH NTSC Single Ended In Ain1, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain1, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH NTSC Single Ended In Ain2, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain2, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH NTSC Single Ended In Ain3, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain3, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH NTSC Single Ended In Ain4, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain4, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##06_YC AUTODETECT##

:YC In Ain1,2, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS 
42 00 08 ; INSEL = YC, Y - Ain1, C - Ain2
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [All ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, pedestal on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:YC In Ain3,4, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS 
42 00 09 ; INSEL = YC, Y - Ain3, C - Ain4
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [All ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, pedestal on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##07_YC INTERLACED TO PROGRESSIVE##

:I2P YC In Ain1,2, 480p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 08 ; INSEL = YC, Y - Ain1, C - Ain2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P YC In Ain1,2, 576p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 08 ; INSEL = YC, Y - Ain1, C - Ain2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P YC In Ain3,4, 480p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 09 ; INSEL = YC, Y - Ain3, C - Ain4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P YC In Ain3,4, 576p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 09 ; INSEL = YC, Y - Ain3, C - Ain4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End 

##08_YPbPr AUTODETECT##

:YPbPr In Ain1,2,3, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes Begin]
42 54 C0 ; AFE IBIAS
42 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [All ADV7280A writes Finished]
56 00 1C ; Power up Encoder
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, pedestal on, PbPr SSAF on, YPbPr out.
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##09_YPbPr Interlaced to Progressive##

:I2P - YPbPr In Ain1,2,3, 480p EAV/SAV, YPbPr Out
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes Begin]
42 54 C0 ; AFE IBIAS
42 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map 
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 00 1C ; Power up Encoder
56 17 02 ; Reset Encoder
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - YPbPr In Ain1,2,3, 576p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes Begin]
42 54 C0 ; AFE IBIAS
42 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map 
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Reset Encoder
56 00 9C ; Power up Encoder
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##10_Program Interrupts##

:Enable Analog Video Lock/Unlock Interrupts:
42 0E 20 ; Enter Interrupt Map
42 44 03 ; Unmask SD_LOCK and SD_UNLOCK interrupts
42 43 03 ; Clear Clear SD_LOCK and SD_UNLOCK interrupts
42 40 D1 ; Set INTRQ pin to drive low when active and remain low until cleared
42 0E 00 ; Enter User Map
End

:Clear Analog Video Lock/Unlock Interrupts:
42 0E 20 ; Enter Interrupt Map
42 43 03 ; Clear Clear SD_LOCK and SD_UNLOCK interrupts
42 0E 00 ; Enter User Map
End
Hi All,
We have verified this behavior in our test bench using the attached script. All the scripts generate the proper video. Kindly verify your settings with this script and let us know the results

Thanks,
Ebin
jon510 on May 18, 2026 7:16 AM in reply to Ebin
0

Hi Ebin,

Thank you for the scripts.

We solved the issue by changing the ADV7280A VBI-to-active-line controls:

42 EB 05
42 EC 05

Previously we had:

42 EB 55
42 EC 55

With 0xEB = 0x05 and 0xEC = 0x05, the unstable chroma artifacts on the first active NTSC line disappear. The output remains in BT.656-4 mode.

Our understanding is that these registers control when comb filtering and color output start after VBI, and our STANAG Class C / NTSC source required this to start one line earlier.

Best regards,
Jonathan
Cancel
Up 0 Down

Reply

Verify Answer

Reject Answer

Cancel
Reply
jon510 on May 18, 2026 7:16 AM in reply to Ebin
0

Hi Ebin,

Thank you for the scripts.

We solved the issue by changing the ADV7280A VBI-to-active-line controls:

42 EB 05
42 EC 05

Previously we had:

42 EB 55
42 EC 55

With 0xEB = 0x05 and 0xEC = 0x05, the unstable chroma artifacts on the first active NTSC line disappear. The output remains in BT.656-4 mode.

Our understanding is that these registers control when comb filtering and color output start after VBI, and our STANAG Class C / NTSC source required this to start one line earlier.

Best regards,
Jonathan
Cancel
Up 0 Down

Reply

Verify Answer

Reject Answer

Cancel
Children
No Data
Popular Forums

Product Forums

Application Forums

Design Center Forums

Highlighted Webinar

Places

Libraries

Upcoming Learning & Events

Challenge Yourself!

What's Brewing

Places

Resources

Visit ContentZone

The Latest Read

New Release

Recent Technical Insights

Products Mentioned

Thread Details

ADV7280A: Unstable chroma on first active line of BT.656 (STANAG Class C / NTSC)
