ADV7280A: Unstable chroma on first active line of BT.656 (STANAG Class C / NTSC)

jon510 on Mar 30, 2026

Thread Summary

The user encountered unstable chroma artifacts on the first active line of NTSC fields when using the ADV7280A with STANAG 3350 Class C composite input and 8-bit embedded BT.656-4 output. The issue was resolved by changing the VBI-to-active-line controls (registers 0xEB and 0xEC) to 0x05, which stabilized the chroma on the first active line without affecting the BT.656-4 output timing.
AI Generated Content

Category: Hardware

Hello,

I am using the ADV7280A with a STANAG 3350 Class C (NTSC RS-170A timing equivalent) composite input and 8-bit embedded BT.656-4 output.

Symptom:
The first active row of one field shows blinking colored dots (unstable chroma) on saturated colors such as SMPTE bars. Luma appears stable. Row 1 and the following rows are clean.

Isolation:
We checked the raw BT.656 output directly with an FPGA Integrated Logic Analyzer (ILA). The ADV7280A outputs 487 active lines, and the chroma variation is already present on the first active line of the raw byte stream before our FPGA crops it to 720x486 lines for the downstream modules.

Attempted fixes:
We tested several documented registers and EngineerZone-recommended initialization sequences, including 0x27, 0x2B to 0x2E, 0x3D, 0x38 to 0x39, and 0xEB to 0xEC, without any change to the first-line behavior. We have also checked with different video sources.

For reference, our baseline ADV7280A configuration is:
0x00 = 0x00
0x02 = 0x14
0x03 = 0x0C
0x04 = 0xBD
0x1D = 0x64
0x0F = 0x00
0x3A = 0x07

Questions:

1. Is this a known ADV7280A behavior for STANAG Class C / non-broadcast NTSC sources, specifically on the first active line of a field?

2. Could this be related to NTSC field-boundary / SCH burst phase behavior, or to how the ADV7280A handles chroma decoding / comb filtering on the first active line?

3. Is there any documented or undocumented register sequence that can improve first-line chroma stability, or is the recommended approach simply to mask this line downstream?

Thanks in advance for the support.

Kind regards,
Jonathan

jon510 on Apr 15, 2026 4:17 AM
0

Hi,

Any idea concerning this request?

Thanks in advance,

Jonathan
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Ebin

on Apr 22, 2026 7:41 AM

Hi Jonathan,

We have verified the output on our test bench using the ADV7280A evaluation hardware. We did not observe any dotted lines on the screen, and the output on the monitor was normal. We have attached the sample scripts used for our validation.

Thanks,

Ebin

Fullscreen ADV7280A_NTSC-m.txt Download

; Advantiv® AVES Blue 3.03.0909 by Analog Devices
; Register capture     22-04-2026 12:06:45
; Device: ADV7280A_Cust
;
; UserMap
42 00 00
42 01 C8
42 02 04
42 03 0C
42 04 07
42 07 7F
42 08 80
42 0A 00
42 0B 00
42 0C 36
42 0D 7C
42 0E 00
42 0F 00
42 10 0F ; Read only
42 11 43 ; Read only
42 12 00 ; Read only
42 13 69 ; Read only
42 14 10
42 15 04
42 17 41
42 18 93
42 19 F1
42 1D 40
42 27 58
42 2B E1
42 2C AE
42 2D F3
42 2E 0D
42 2F F5
42 30 09
42 31 02
42 32 41
42 33 84
42 34 00
42 35 02
42 36 00
42 37 81
42 38 80
42 39 C0
42 3A 00
42 3D 22
42 41 01
42 48 00
42 49 00
42 4A 00
42 4B 00
42 4C 00
42 4D EF
42 4E 08
42 50 08
42 51 24
42 52 CD
42 53 4E
42 54 80
42 59 00
42 5A D0
42 5D 6D
42 5E 6D
42 60 10
42 6A 00
42 6B 92
42 70 00
42 71 00
42 72 00
42 73 20
42 74 00
42 75 00
42 76 00
42 77 00
42 78 00
42 79 00
42 7A F8
42 7B 00
42 7C 00
42 7D 00
42 7E 00
42 7F 00
42 8F 00
42 90 00 ; Read only
42 91 00 ; Read only
42 92 00 ; Read only
42 93 00 ; Read only
42 94 00 ; Read only
42 95 00 ; Read only
42 96 00 ; Read only
42 97 00 ; Read only
42 98 00 ; Read only
42 99 00 ; Read only
42 9A 00 ; Read only
42 9B 00 ; Read only
42 9C 00 ; Read only
42 9D 00 ; Read only
42 B2 00
42 C3 00
42 C4 20
42 DC AC
42 DD 4C
42 DE 08 ; Read only
42 DF 08 ; Read only
42 E1 80
42 E2 80
42 E3 80
42 E4 80
42 E5 25
42 E6 04
42 E7 63
42 E8 65
42 E9 14
42 EA 63
42 EB 55
42 EC 55
42 F3 00
42 F4 15
42 F8 00
42 F9 03
42 FB 40
42 FC 04
42 FD 00
;
; UserSubMap1
42 40 90
42 42 7E ; Read only
42 43 A4
42 44 FF
42 45 B6 ; Read only
42 46 12 ; Read only
42 47 00
42 48 00
42 49 00 ; Read only
42 4A 00 ; Read only
42 4B 00
42 4C 00
42 4D EF ; Read only
42 4E 08 ; Read only
42 4F 08
42 50 08
42 51 24 ; Read only
42 53 4E ; Read only
42 54 80
42 55 00
42 60 10
42 61 00
42 62 20
42 63 D0
42 64 10
42 65 06
42 66 28
42 67 03
42 68 01
42 69 00
42 6A 00
42 6B 92
42 6C 03
42 6D 00
42 6E 00
42 6F 00
42 70 00
42 71 00
42 72 00
42 73 20
42 74 00
42 75 00
42 76 00
42 77 00
42 78 00
42 79 00 ; Read only
42 7A F8 ; Read only
42 7D 00 ; Read only
42 7E 00 ; Read only
42 7F 00 ; Read only
42 81 51
42 83 00 ; Read only
42 84 0C ; Read only
42 85 02 ; Read only
42 86 03 ; Read only
42 87 63 ; Read only
42 88 5A ; Read only
42 89 08 ; Read only
42 8A 10 ; Read only
42 8B 01 ; Read only
42 8C 40 ; Read only
42 8D 20 ; Read only
42 8E 40 ; Read only
42 8F 00 ; Read only
42 90 00 ; Read only
42 91 00 ; Read only
42 92 00 ; Read only
42 93 00 ; Read only
42 94 00 ; Read only
42 95 00 ; Read only
42 96 00 ; Read only
42 97 00 ; Read only
42 98 00 ; Read only
42 99 00 ; Read only
42 9A 00 ; Read only
42 9B 00 ; Read only
42 9C 00
;
; UserSubMap2
42 65 06
42 66 28
42 67 03
42 68 01
42 69 00
42 80 51
42 83 00
42 84 0C
42 85 02
42 86 03
42 87 63
42 92 00
42 C8 00 ; Read only
42 C9 04
42 CA 00
42 CB 00
42 CC 69
42 CD 00
42 CE 01
42 CF B4
42 D0 00
42 D1 10 ; Read only
42 D2 FF ; Read only
42 D3 FF
42 D4 7F
42 D5 7F
42 D6 3E
42 D7 08 ; Read only
42 D8 3C ; Read only
42 D9 08
42 DA 3C
42 DB 9B
42 DC AC
42 DD 4C
42 DE 08
42 E0 14
42 E1 80
42 E2 80
42 E3 80
42 E4 80
42 E5 25
42 E6 04
42 E7 63 ; Read only
;
; VPP
84 41 00
84 55 00
84 5B 00

jon510 on May 13, 2026 3:57 AM
0

Hi Ebin,

Thank you for the sample scripts.

We applied the ADV7280A NTSC script you provided. On our setup, the issue does not appear to be fully resolved.

With the provided script, the output now shows several dark/black rows at the top of the frame. However, the unstable dotted/noisy line is still visible on the first real video content row immediately after those black rows. I have attached a frame capture showing this behavior.

If we restore our BT.656-4 output configuration, the black rows disappear, but the same unstable line appears on the first active row of the image.

So it looks like the provided script changes the output framing and moves the first visible content line downward, but the first decoded active video line still has the instability.

Can you please confirm whether your validation was done with BT.656-4 output enabled and with the first real active video row visible?

Could you provide a configuration that keeps BT.656-4 output timing, does not add the top black rows, and stabilizes the first active content line?

Best regards,
Jonathan

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Ebin

on May 15, 2026 6:21 AM

Fullscreen ADV7280A_CUST-VER.5.0.txt Download

;;DecoderLegacySupport = True;;
;;Reset = False;;
;;ReadInterface = True;;

##ASettings##
:Customer Version 5.0 August 2017 ADV7280A :
End

##01_Free-run Mode##

:Free-run, 480i 60Hz YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Free-run, Color Bars 480p YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write 
42 81 51 ; ADI Required Write 
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:Free-run, 576i 50Hz YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 84 ; Force standard to PAL
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Free-run, Color Bars 576p YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS 
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 84 ; Force standard to PAL
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write 
42 81 51 ; ADI Required Write 
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##02_CVBS AUTODETECT##

:Autodetect CVBS Single Ended In Ain 1, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Autodetect CVBS Single Ended In Ain 2, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Autodetect CVBS Single Ended In Ain 3, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:Autodetect CVBS Single Ended In Ain 4, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##03_CVBS INTERLACED TO PROGRESSIVE##

:I2P - NTSC In Ain1,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain1, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - NTSC In Ain2,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain2, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - NTSC In Ain3,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain3, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - NTSC In Ain4,YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder writes begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - PAL In Ain4, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##04_CVBS FAST Switch##

:FAST Switch CVBS Single Ended In Ain1, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:FAST Switch CVBS Single Ended In Ain2, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:FAST Switch CVBS Single Ended In Ain3, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:FAST Switch CVBS Single Ended In Ain4, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##05_CVBS FAST Switch I2P##

:I2P FAST SWITCH NTSC Single Ended In Ain1, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain1, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 00 ; CVBS in on AIN1
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH NTSC Single Ended In Ain2, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain2, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 01 ; CVBS in on AIN2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH NTSC Single Ended In Ain3, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain3, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 02 ; CVBS in on AIN3
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH NTSC Single Ended In Ain4, YPbPr Out (480p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P FAST SWITCH PAL Single Ended In Ain4, YPbPr Out (576p EAV/SAV):
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1] 
42 9C FF ; Reset Current Clamp Circuitry [step2] 
42 0E 00 ; Enter User Sub Map
42 0E 80 ; ADI Required Write [Fast Switch]
42 D9 44 ; ADI Required Write [Fast Switch]
42 0E 40 ; Select User Sub Map 2 [Fast Switch]
42 E0 01 ; Select fast Switching Mode [Fast Switch]
42 0E 00 ; Select User Map [Fast Switch]
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280A VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes finished]
56 17 02 ; Software Reset  [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##06_YC AUTODETECT##

:YC In Ain1,2, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS 
42 00 08 ; INSEL = YC, Y - Ain1, C - Ain2
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [All ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, pedestal on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

:YC In Ain3,4, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS 
42 00 09 ; INSEL = YC, Y - Ain3, C - Ain4
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [All ADV7280A writes finished]
56 00 1C ; Power up DACs and PLL [Encoder Writes Begin]
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, pedestal on, PbPr SSAF on, YPbPr out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##07_YC INTERLACED TO PROGRESSIVE##

:I2P YC In Ain1,2, 480p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 08 ; INSEL = YC, Y - Ain1, C - Ain2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P YC In Ain1,2, 576p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 08 ; INSEL = YC, Y - Ain1, C - Ain2
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P YC In Ain3,4, 480p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 09 ; INSEL = YC, Y - Ain3, C - Ain4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P YC In Ain3,4, 576p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 53 CE ; AFE IBIAS
42 00 09 ; INSEL = YC, Y - Ain3, C - Ain4
42 0E 80 ; ADI Required Write 
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Software Reset [Encoder Writes Begin]
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End 

##08_YPbPr AUTODETECT##

:YPbPr In Ain1,2,3, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes Begin]
42 54 C0 ; AFE IBIAS
42 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [All ADV7280A writes Finished]
56 00 1C ; Power up Encoder
56 01 00 ; SD only mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, pedestal on, PbPr SSAF on, YPbPr out.
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

##09_YPbPr Interlaced to Progressive##

:I2P - YPbPr In Ain1,2,3, 480p EAV/SAV, YPbPr Out
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes Begin]
42 54 C0 ; AFE IBIAS
42 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map 
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 00 1C ; Power up Encoder
56 17 02 ; Reset Encoder
56 00 9C ; Power up DAC's and PLL
56 01 70 ; ED at 54MHz input
56 30 04 ; 525p at 59.94 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

:I2P - YPbPr In Ain1,2,3, 576p EAV/SAV, YPbPr Out:
delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
56 17 02 ; Reset Encoder
delay 10 ; Wait 10ms 
42 0F 00 ; Exit Power Down Mode [ADV7280A writes Begin]
42 54 C0 ; AFE IBIAS
42 00 0C ; INSEL = YPbPr, Y=Ain1, Pb=Ain2, Pr=Ain3
42 0E 80 ; ADI Required Write
42 9C 00 ; Reset Current Clamp Circuitry [step1]
42 9C FF ; Reset Current Clamp Circuitry [step2]
42 0E 00 ; Enter User Sub Map
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ pad, Enable SFL & VS pin
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver
42 FD 84 ; Set VPP Map 
84 A3 00 ; ADI Required Write
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280A writes Finished]
56 17 02 ; Reset Encoder
56 00 9C ; Power up Encoder
56 01 70 ; ED at 54MHz input
56 30 1C ; 625p at 50 Hz with Embedded Timing
56 31 01 ; Pixel Data Valid [Encoder Writes finished]
End

##10_Program Interrupts##

:Enable Analog Video Lock/Unlock Interrupts:
42 0E 20 ; Enter Interrupt Map
42 44 03 ; Unmask SD_LOCK and SD_UNLOCK interrupts
42 43 03 ; Clear Clear SD_LOCK and SD_UNLOCK interrupts
42 40 D1 ; Set INTRQ pin to drive low when active and remain low until cleared
42 0E 00 ; Enter User Map
End

:Clear Analog Video Lock/Unlock Interrupts:
42 0E 20 ; Enter Interrupt Map
42 43 03 ; Clear Clear SD_LOCK and SD_UNLOCK interrupts
42 0E 00 ; Enter User Map
End

Hi All,
We have verified this behavior in our test bench using the attached script. All the scripts generate the proper video. Kindly verify your settings with this script and let us know the results

Thanks,
Ebin

jon510 on May 18, 2026 7:16 AM in reply to Ebin
0

Hi Ebin,

Thank you for the scripts.

We solved the issue by changing the ADV7280A VBI-to-active-line controls:

42 EB 05
42 EC 05

Previously we had:

42 EB 55
42 EC 55

With 0xEB = 0x05 and 0xEC = 0x05, the unstable chroma artifacts on the first active NTSC line disappear. The output remains in BT.656-4 mode.

Our understanding is that these registers control when comb filtering and color output start after VBI, and our STANAG Class C / NTSC source required this to start one line earlier.

Best regards,
Jonathan
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Thread Details

ADV7280A: Unstable chroma on first active line of BT.656 (STANAG Class C / NTSC)

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