Glitch at the end of Vertical Sync pulse when digitizing interlaced graphics signals

Hi,

  Please refer this thread https://ez.analog.com/video/f/q-a/7388/adv7842-vertical-sync-anomaly?utm_source=chatgpt.com Here also customer discussed about the same Vsync glitch issue and resolved.

Thanks,

Poornima

Hi PoornimaSubramani,

I read the thread you suggested, and if I understood correctly, writing the value 0x0001 into the CP_END_VS_EVEN register should remove the glitch.
I tried this solution, but nothing changes. The glitch is still there, I also tried writing other values in the CP_START_VS, CP_END_VS, CP_START_VS_EVEN and CP_STOP_VS_EVEN registers, but nothing changes to the position of the VS sync pulse, it is as if these registers do not work.
Is there another register that needs to be set (some kind of an enable register) to make the value in the CP_START_VS_EVEN register to be applied to the VS out signal?

Thanks,

Stefaan

Hi Poornima,

I believe I found the solution to my problem.

When writing in register CP 0x8F (CH1_FR_LL[10:8]) I accidentally cleared the undocumented bit 6, which contains 1 as default value. It seems that, if you clear this bit, the glitch starts to appear. When keeping this bit set, the VS sync pulse looks normal.

Kind regards,

Stefaan.

Hi,

Kindly note that, The synchronous signals aligned with the pixel data can be captured with the LLC clock (But the asynchronous signals are not aligned with the video pixel data. However, they are valid even if the LLC is not locked to input video).

Synchronous signal accompany the data and determine the position of the vertical synchronization with pixel accuracy. As a prerequisite, the LLC clock must be locked and this requires PRIM_MODE[3:0], VID_STD[5:0], and other registers to be configured correctly so please ensure your synchronization related registers configuration - For Example - HS_OUT_SEL, VS_OUT_SEL at https://www.analog.com/media/en/technical-documentation/user-guides/UG-214.pdf

Thanks,

Poornima

Hi,

  Thanks for letting us know.

Thanks,

Poornima