ADV7181C Register Settings for STANAG3350 Signals

Hi,

  Please refer this document for PLL settings https://www.analog.com/en/resources/app-notes/an-0978.html

Thanks,

Poornima

Thank you Poornima,

But this document is not for ADV7181C. Does it matter?

My main question was why does Table 11 in the User Manual of ADV7181C does not list a lines per frame of 625?

Thanks and regards,

Paul

Hi Ebin,

1. Kindly verify the HS and VS timing values. - HSync = 64uS Verified with Scope. Vsync, I could not to it properly.
2. Please enable the Free-Run mode on your device.   It is already enabled
3. Could you also confirm the LLC value? - 27.003MHz

We are having tough time in resolving this issue. Main problem with this Decoder is that the User Manual is having lot of typo/mistakes and we can not resolve such issues without ADI's help.

We are getting some output when so called "ADI Recommended Settings" in a a few registers are used and we have no idea what does those registers do.

We also see some changes in register 0x02 (which is mentioned as 'Reserved' in the user manual). If we update this register with value 0x07, we see some changes. But image is getting blurred.

Could you please let us know the the correct procedure to manually generate 27MHz LLC clock from the Decoder for SD Mode?

Only the register changes in 0x87 and 0x88 is sufficient?

Thanks and regards,

Paul

Hi Paul,

    As per the expert recommendation,  "For best performance we recommend the use of a 28.6363MHz crystal". Please refer 7.3.1 section of the Hardware user manual for the stable generation of the LLC.
     
Thanks,
Ebin

Hi Ebin,

Even though, the user manual says that for Best Performance, 28.6363MHz, our observation is that:

(1) For NTSC, the best performance is with 28.6363MHz because it is an integer Multiple of NTSC Color Sub Carrier 3.579545MHz

28.636363/3.579545= 8.0000

(2) For PAL (Sub Carrier = 4.43361875MHz), the 28.6363MHz is not an integer Multiple. (28.6363/4.43361875 = 6.45889996744)

But if we use 27MHz Oscillator, we can get better output:

27/4.43361875 = 6.08983350226

Since we have not much information about the internals of Chip, we are struggling with this for the last 2 months.

Most of the critical registers in the User Manual are mentioned as RSVD. Moreover there are mistakes in the User Manual which makes the problem worser.

If you can help with the register settings for STANAG 3350 B with 27MHz Crystal/Oscillator it would have been a lot of help.

Thanks and regards,

Paul

Hi Paul,

    Use a 17.734475 MHz oscillator instead of 28.636363 MHz for PAL. This allows an integer division ratio (÷4), resulting in 4.43361875 MHz. Please check the settings accordingly. Please give proper values in the 0x87,0x88 and 0x8A Registers.

Thanks,
Ebin

Hi Ebin,

In that case, can you share the script for this change?

Or only 0x87, 0x88 and 0x8A are required?

What should be the value for 0x1D?

Thanks and regards,

Paul

Hi Paul,
    We can select the divider value as 4 in the register mentioned above for 17MHz, No option is available in the 0x1D register. As you mentioned earlier, with a 27 MHz oscillator (27 / 4.43361875 = 6.08983350226), we can achieve better PAL output. Could you please check the output for different PLL_QPUMP[2:0] settings in register 0x3C?
    
Thanks,
Ebin

Hi Ebin,

I tried many values. But I am not getting exact 27.000MHz. It is not precisely locking to that frequency even with a 27.000MHz Frequency. We are using 27 MHz Oscillator with output 3.3V (As per Datasheet Page 10 of 20, Version E).

In some posts, and User Manual, I have seen that Oscillator Power is 1.8V . Does it mean that we will have to use 1.8V oscillator? 

I am also confused why PLL is not precisely locking to 27.000MHz despite adding more decoupling capacitors to PVDD.

Thanks and regards,

Paul

Hi Paul,

Regarding the oscillator supply voltage, please follow the value specified in the datasheet.

For PLL locking, please refer to the FAQ link below:
 https://ez.analog.com/video/w/documents/716/how-to-tell-if-the-adv7180-adv7182-adv728x-has-locked-to-a-video-source

Thanks,
Ebin

These are the settings I've used for the RGB video you describe, for the past 15 years.

Also ensure the capacitors on the ELPF input are COG dielectric, not X7R as they drift a lot with temperature.

Hi,

  Apologies for the delayed response, 

Some sections of the datasheet and also in ADI EngineerZOne, it was mentioned that we should use 1.8V External Oscillator. So we are in confusion.

    Yes, in the datasheet it is mentioned as 3.3V, but as per the expert's comment, it is mentioned as 1.8V. Please follow our expert's suggestion.

     Reference:  How Do I Use An External Oscillator to Clock the ADV7182 ? 

Also, PVDD is very important for maintaining the video stability.

  Ideally it should be ferrite bead isolated from other supplies and the data sheet reference schematic does not show this which is OK if the PVDD source is very clean. 

  First check PVDD noise both high frequency and lower frequencies around the horizontal rates.  If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

Also make sure with below things,

 1) First verify the PVDD_1.8V for the ELPF remains stable and clean when the problem shows up.

 2) Check that all voltages are clean and stable.

 3) Try C0G (NPO) material caps since it as better temperature coefficient.

Thanks,

Poornima S

Hi,

  Apologies for the delayed response, 

Some sections of the datasheet and also in ADI EngineerZOne, it was mentioned that we should use 1.8V External Oscillator. So we are in confusion.

    Yes, in the datasheet it is mentioned as 3.3V, but as per the expert's comment, it is mentioned as 1.8V. Please follow our expert's suggestion.

     Reference:  How Do I Use An External Oscillator to Clock the ADV7182 ? 

Also, PVDD is very important for maintaining the video stability.

  Ideally it should be ferrite bead isolated from other supplies and the data sheet reference schematic does not show this which is OK if the PVDD source is very clean. 

  First check PVDD noise both high frequency and lower frequencies around the horizontal rates.  If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

Also make sure with below things,

 1) First verify the PVDD_1.8V for the ELPF remains stable and clean when the problem shows up.

 2) Check that all voltages are clean and stable.

 3) Try C0G (NPO) material caps since it as better temperature coefficient.

Thanks,

Poornima S