ADV7181C Register Settings for STANAG3350 Signals

Hi,

  Please refer this document for PLL settings https://www.analog.com/en/resources/app-notes/an-0978.html

Thanks,

Poornima

Thank you Poornima,

But this document is not for ADV7181C. Does it matter?

My main question was why does Table 11 in the User Manual of ADV7181C does not list a lines per frame of 625?

Thanks and regards,

Paul

Hi Poornima,

The values you suggested are near to 60Hz vertical frequency, right? (Highlighted with yellow color)

Then how does it suit for 50Hz?

Thanks and regards,

Paul

Hi,

  Sorry, It was highlighted incorrectly.
  As stated, to make it 50 Hz, Please try adjusting the "PLL_Divisor, VCO_Range, and Charge Pump registers."

Thanks,

Poornima 

Hi Poornima,

Can we use 27MHz Crystal for 28.63636MHz for ADV7181C?

We are suspecting that PAL 28.63636 MHz is not an integer multiple of PAL Subcarrier frequency. However, it matches with NTSC Sub Carrier.

We are suspecting if that fractional difference is creating the issue with PAL signals?

If yes, could you please let us know which all registers have to be changed other than 0x1D?

Thanks and regards,

Paul

Hi,

    Please use 27 MHz in your system for both PAL and NTSC and let us know the status.

Thanks,

Ebin

Hi Ebin,

Please let us know the registers we need to change other than 0x1D

Thanks and regards,

Paul

Hi ,

Please find the related register details bellow:

Autodetect enable : Register Address : 0x07
We can force the autodetect algorithm to only expect a PAL signal. See the "Autodetect enable" bits (User Map register 0x07). If you know the particular type of PAL (PAL-I, PAL-60, PAL-M etc) you can program the ADV7181c autodetect algorithm to only look for that PAL standard. This way, the ADV7181c knows what the color subcarrier frequency should be. This should make it easier for the ADV7181c to lock to this non-standard signal.

Primary Mode : Register Address : 0x05
PRIM_MODE[3:0] Selects the primary mode of operation of the decoder. Used with VID_STD[3:0]

Video Standard : Register Address : 0x06
VID_STD[3:0] Sets the input and output Video standards dependent on PRIM_MODE[2:0]

Manual PLL Divider Ratio Value
PLL_DIV_MAN_EN Enable Manual PLL Ratio Value (CP), Address 0x87, [7]
PLL_DIV_RATIO[11:0] Address 0x87, [3:0]; Address 0x88, [7:0]

Crystal mode :
Configure in 0x1D register for 27Mhz/28Mhz.

Thanks,
Ebin

Hi Ebin,

Thank you for your supports. We have changed the Crystal to 27MHz and did not see improvement.

One of the doubt we are having is what value we should program to 0X0 Register. By default it is in CVBS Mode.

Shouldn't we write INPUT CONTROL(0x00) = 0x09 value there to take the STANAG 3350 B input?

One of the strange thing we observed in PAL mode is when we write 0x07 to register 0x02 (Mentioned as RSVD in Manual), we see slight change.

Thanks and regards,

Paul

Hi ,

   Thank you for the information. Please verify the register settings I mentioned above for 28 MHz.As the expert recommended "In some earlier devices a 27MHz crystal was used but this was changed to 28.63636 to avoid inter modulation noise between the sampling clock and line lock clock. For best performance we recommend the use of a 28.6363MHz crystal.

Refer this FAQ  RE: How Do I Use An External Oscillator to Clock the ADV7182 ? 

Also refer expert comment at thread  RE: ADV7181C: unstable LLC, hot case 

>>>Shouldn't we write INPUT CONTROL(0x00) = 0x09 value there to take the STANAG 3350 B input?
    Yes . kindly apply the settings and let us know the status.

Thanks,
Ebin

Hi Ebin,

We were testing with ADV7181C EVK with PAL input and we are seeing the similar noise with EVK also.

However, we see a change one of the register 0x02 (mentioned as RSVD in User Manual of ADV7181C) is showing slight changes as follows.

(1) Register 0x02   - Value written 0x00     -----> Image is sharper but the shivering noise is more visible

(2) Register 0x02   - Value written 0x07     -----> Image is lost sharpness, but shivering of pixels are less.

Since, this issue is seen in the EVK also, can you throw some lights on register settings which may improve the situation?

Thanks and regards,

Paul

Hi Paul,
    Thanks for the update.
Kindly Enable the below filters in ADV7181C and let us know the status.
1. DNR_EN Digital Noise Reduction Enable 0xD[5]
2. Luma Peaking Gain 0xFB[7:0]
3. Enable Anti Alias Filters 0xF3[3:0]

Thanks,
Ebin

Hi Paul,
    Thanks for the update.
Kindly Enable the below filters in ADV7181C and let us know the status.
1. DNR_EN Digital Noise Reduction Enable 0xD[5]
2. Luma Peaking Gain 0xFB[7:0]
3. Enable Anti Alias Filters 0xF3[3:0]

Thanks,
Ebin

Hi Ebin,

DNR_EN is already enabled.

We tried Luma Peaking Gain and Anti Alias Filters - No change.

Thanks and regards,

Paul

Hi Paul,

     Could you please check the following items in your setup and share the status with us?

1. Kindly verify the HS and VS timing values.
2. Please enable the Free-Run mode on your device.
3. Could you also confirm the LLC value?

Thanks,
Ebin

Hi Ebin,

1. Kindly verify the HS and VS timing values. - HSync = 64uS Verified with Scope. Vsync, I could not to it properly.
2. Please enable the Free-Run mode on your device.   It is already enabled
3. Could you also confirm the LLC value? - 27.003MHz

We are having tough time in resolving this issue. Main problem with this Decoder is that the User Manual is having lot of typo/mistakes and we can not resolve such issues without ADI's help.

We are getting some output when so called "ADI Recommended Settings" in a a few registers are used and we have no idea what does those registers do.

We also see some changes in register 0x02 (which is mentioned as 'Reserved' in the user manual). If we update this register with value 0x07, we see some changes. But image is getting blurred.

Could you please let us know the the correct procedure to manually generate 27MHz LLC clock from the Decoder for SD Mode?

Only the register changes in 0x87 and 0x88 is sufficient?

Thanks and regards,

Paul

Hi Paul,

    As per the expert recommendation,  "For best performance we recommend the use of a 28.6363MHz crystal". Please refer 7.3.1 section of the Hardware user manual for the stable generation of the LLC.
     
Thanks,
Ebin

Hi Ebin,

Even though, the user manual says that for Best Performance, 28.6363MHz, our observation is that:

(1) For NTSC, the best performance is with 28.6363MHz because it is an integer Multiple of NTSC Color Sub Carrier 3.579545MHz

28.636363/3.579545= 8.0000

(2) For PAL (Sub Carrier = 4.43361875MHz), the 28.6363MHz is not an integer Multiple. (28.6363/4.43361875 = 6.45889996744)

But if we use 27MHz Oscillator, we can get better output:

27/4.43361875 = 6.08983350226

Since we have not much information about the internals of Chip, we are struggling with this for the last 2 months.

Most of the critical registers in the User Manual are mentioned as RSVD. Moreover there are mistakes in the User Manual which makes the problem worser.

If you can help with the register settings for STANAG 3350 B with 27MHz Crystal/Oscillator it would have been a lot of help.

Thanks and regards,

Paul

Hi Paul,

    Use a 17.734475 MHz oscillator instead of 28.636363 MHz for PAL. This allows an integer division ratio (÷4), resulting in 4.43361875 MHz. Please check the settings accordingly. Please give proper values in the 0x87,0x88 and 0x8A Registers.

Thanks,
Ebin

Hi Ebin,

In that case, can you share the script for this change?

Or only 0x87, 0x88 and 0x8A are required?

What should be the value for 0x1D?

Thanks and regards,

Paul

Hi Paul,
    We can select the divider value as 4 in the register mentioned above for 17MHz, No option is available in the 0x1D register. As you mentioned earlier, with a 27 MHz oscillator (27 / 4.43361875 = 6.08983350226), we can achieve better PAL output. Could you please check the output for different PLL_QPUMP[2:0] settings in register 0x3C?
    
Thanks,
Ebin

Hi Ebin,

I tried many values. But I am not getting exact 27.000MHz. It is not precisely locking to that frequency even with a 27.000MHz Frequency. We are using 27 MHz Oscillator with output 3.3V (As per Datasheet Page 10 of 20, Version E).

In some posts, and User Manual, I have seen that Oscillator Power is 1.8V . Does it mean that we will have to use 1.8V oscillator? 

I am also confused why PLL is not precisely locking to 27.000MHz despite adding more decoupling capacitors to PVDD.

Thanks and regards,

Paul

Hi Paul,

Regarding the oscillator supply voltage, please follow the value specified in the datasheet.

For PLL locking, please refer to the FAQ link below:
 https://ez.analog.com/video/w/documents/716/how-to-tell-if-the-adv7180-adv7182-adv728x-has-locked-to-a-video-source

Thanks,
Ebin