ADV7181C Register Settings for STANAG3350 Signals

Hi,

  Please refer this document for PLL settings https://www.analog.com/en/resources/app-notes/an-0978.html

Thanks,

Poornima

Thank you Poornima,

But this document is not for ADV7181C. Does it matter?

My main question was why does Table 11 in the User Manual of ADV7181C does not list a lines per frame of 625?

Thanks and regards,

Paul

Hi Poornima,

Fundamental Confusion is:

1. STANAG  3350 B signals are Analog RGB Video and Best Match is VGA than YPbPr Component Video.

2. If that is true, the best match will be Graphics RGB Option and unfortunately, we do not see an option for 50Hz (which will match with PAL Refresh rate). But 60Hz option is there.

Please let us know your suggestions. One of the observation is that when we feed NTSC signal, we do not see the jitter as I mentioned in the starting of the thread. 

May be if you can give us a script for SCART or VGA with 50Hz option may help. Please correct me if I am wrong

Thanks and regards,

Paul

Hi,

  I suggested 1x clock for 'VID_STD' configuration since the clock will be doubled for '1440×480' (2x Oversampling).

Thanks,

Poornima

Yes. 0xC3 = 0x56 and 0xC4 =0x84

Hi,

  Are you experiencing this “jittering/shivering” issue with standard formats as well, or only with STANAG 3350 formats ?

Thanks,

Poornima

Hi Poornima,

We are getting this issue with PAL Related inputs - PAL CVBS input and STANAG 3350 B which is also having PAL timing.

• One change we are having from EVK is that we are using 3.3V External Oscillator of 28.6363MHz 50ppm instead of XTAL.
• Some sections of the datasheet and also in ADI EngineerZOne, it was mentioned that we should use 1.8V External Oscillator. So we are in confusion.
• I also see that for VGA, there is no option for 50Hz - Only 60Hz and some uncommon Vertical Frequency only supported.

Thanks and regards,

Paul

Hi,

  Kindly note that the ADV7180 datasheet specifies a 1.8 V requirement, whereas the ADV7181C datasheet does not. Therefore, we need to operate each device according to its respective part specifications.

 I also see that for VGA, there is no option for 50Hz - Only 60Hz and some uncommon Vertical Frequency only supported.

  Yes, we do not have an option for a 50 Hz frame rate in the VGA formats. Please try below PLL settings for 50Hz,

Thanks,

Poornima

Hi Poornima,

Thanks.

Meantime, we want to try the settings in ADV7181C EVK first and for some reason, the "ADV Register Control" downloaded from FTP is not working properly after installation. - The Software is not able to detect USB and also Script file is not getting loaded.

Is it possible to share the Software in this link?

Thanks and regards,

Paul

Hi,

Please make sure you are following the instructions according to "ADV7181C_EVAL_NOTE_RevA.pdf" at 6406.ADV7181C_Evaluation_Board_Documents.zip

And also crosscheck with below attached ADV register control software user guide (Here you can find the Software debugging Procedure), this would provide a information between user interface to perform register-level control of Analog Devices Video decoders/encoders.

  PDF

Also note that, Try to install a 'ADV Register Control software' with “Run as administrator” option.

Thanks,

Poornima

Hi Poornima,

The values you suggested are near to 60Hz vertical frequency, right? (Highlighted with yellow color)

Then how does it suit for 50Hz?

Thanks and regards,

Paul

Hi,

  Sorry, It was highlighted incorrectly.
  As stated, to make it 50 Hz, Please try adjusting the "PLL_Divisor, VCO_Range, and Charge Pump registers."

Thanks,

Poornima 

Hi,

  Sorry, It was highlighted incorrectly.
  As stated, to make it 50 Hz, Please try adjusting the "PLL_Divisor, VCO_Range, and Charge Pump registers."

Thanks,

Poornima 

Hi Poornima,

Can we use 27MHz Crystal for 28.63636MHz for ADV7181C?

We are suspecting that PAL 28.63636 MHz is not an integer multiple of PAL Subcarrier frequency. However, it matches with NTSC Sub Carrier.

We are suspecting if that fractional difference is creating the issue with PAL signals?

If yes, could you please let us know which all registers have to be changed other than 0x1D?

Thanks and regards,

Paul

Hi,

    Please use 27 MHz in your system for both PAL and NTSC and let us know the status.

Thanks,

Ebin

Hi Ebin,

Please let us know the registers we need to change other than 0x1D

Thanks and regards,

Paul

Hi ,

Please find the related register details bellow:

Autodetect enable : Register Address : 0x07
We can force the autodetect algorithm to only expect a PAL signal. See the "Autodetect enable" bits (User Map register 0x07). If you know the particular type of PAL (PAL-I, PAL-60, PAL-M etc) you can program the ADV7181c autodetect algorithm to only look for that PAL standard. This way, the ADV7181c knows what the color subcarrier frequency should be. This should make it easier for the ADV7181c to lock to this non-standard signal.

Primary Mode : Register Address : 0x05
PRIM_MODE[3:0] Selects the primary mode of operation of the decoder. Used with VID_STD[3:0]

Video Standard : Register Address : 0x06
VID_STD[3:0] Sets the input and output Video standards dependent on PRIM_MODE[2:0]

Manual PLL Divider Ratio Value
PLL_DIV_MAN_EN Enable Manual PLL Ratio Value (CP), Address 0x87, [7]
PLL_DIV_RATIO[11:0] Address 0x87, [3:0]; Address 0x88, [7:0]

Crystal mode :
Configure in 0x1D register for 27Mhz/28Mhz.

Thanks,
Ebin

Hi Ebin,

Thank you for your supports. We have changed the Crystal to 27MHz and did not see improvement.

One of the doubt we are having is what value we should program to 0X0 Register. By default it is in CVBS Mode.

Shouldn't we write INPUT CONTROL(0x00) = 0x09 value there to take the STANAG 3350 B input?

One of the strange thing we observed in PAL mode is when we write 0x07 to register 0x02 (Mentioned as RSVD in Manual), we see slight change.

Thanks and regards,

Paul

Hi ,

   Thank you for the information. Please verify the register settings I mentioned above for 28 MHz.As the expert recommended "In some earlier devices a 27MHz crystal was used but this was changed to 28.63636 to avoid inter modulation noise between the sampling clock and line lock clock. For best performance we recommend the use of a 28.6363MHz crystal.

Refer this FAQ  RE: How Do I Use An External Oscillator to Clock the ADV7182 ? 

Also refer expert comment at thread  RE: ADV7181C: unstable LLC, hot case 

>>>Shouldn't we write INPUT CONTROL(0x00) = 0x09 value there to take the STANAG 3350 B input?
    Yes . kindly apply the settings and let us know the status.

Thanks,
Ebin

Hi Ebin,

We were testing with ADV7181C EVK with PAL input and we are seeing the similar noise with EVK also.

However, we see a change one of the register 0x02 (mentioned as RSVD in User Manual of ADV7181C) is showing slight changes as follows.

(1) Register 0x02   - Value written 0x00     -----> Image is sharper but the shivering noise is more visible

(2) Register 0x02   - Value written 0x07     -----> Image is lost sharpness, but shivering of pixels are less.

Since, this issue is seen in the EVK also, can you throw some lights on register settings which may improve the situation?

Thanks and regards,

Paul

Hi Paul,
    Thanks for the update.
Kindly Enable the below filters in ADV7181C and let us know the status.
1. DNR_EN Digital Noise Reduction Enable 0xD[5]
2. Luma Peaking Gain 0xFB[7:0]
3. Enable Anti Alias Filters 0xF3[3:0]

Thanks,
Ebin

Hi Ebin,

DNR_EN is already enabled.

We tried Luma Peaking Gain and Anti Alias Filters - No change.

Thanks and regards,

Paul

Hi Paul,

     Could you please check the following items in your setup and share the status with us?

1. Kindly verify the HS and VS timing values.
2. Please enable the Free-Run mode on your device.
3. Could you also confirm the LLC value?

Thanks,
Ebin