We are encountering an issue with the ADV7281 where the clock line does not transition to the LP11 state when enabling CSI Tx at low temperatures (below -10°C).
init_driver():
...
start_video_stream():
// Power up MIPI D-phy
CSI MAP DPHY_PWDN_CTL 0x02
// ADI Required Write
CSI map D2 0xF7
CSI map D8 0x65
CSI map E0 0x09
CSI map 2C 0x00
// CSI Tx power-up
CSI MAP CSITX_PWRDN 0x00
stop_video_stream():
// Power up MIPI D-phy
CSI MAP DPHY_PWDN_CTL 0x03
// CSI Tx power-up
CSI MAP CSITX_PWRDN 0x80
At normal temperatures, the above sequence works as expected(adv7281_working_case.png). In this case, the CSI Rx detects the clock start, and the scope shows proper transitions: CLK inactive -> CLK LP -> CLK HS.
At temperatures below -10°C, the same sequence fails. The CSI Rx does not detect the clock start and The scope shows a transition from CLK inactive -> CLK HS but skips the CLK LP state. (adv7281_error_case.png)
Then we have discovered that the following sequence works even if low temperature.
init_driver():
...
// Power up MIPI D-phy
CSI MAP DPHY_PWDN_CTL 0x02
// ADI Required Write
CSI map D2 0xF7
CSI map D8 0x65
CSI map E0 0x09
CSI map 2C 0x00
start_video_stream():
// CSI Tx power-up
CSI MAP CSITX_PWRDN 0x00
stop_video_stream():
// CSI Tx power-up
CSI MAP CSITX_PWRDN 0x80
The key difference here is that there is a delay between init_driver() and start_video_stream().
During this delay, the scope shows the clock transitioning from CLK inactive -> CLK LP. When start_video_stream() is executed, the CSI Rx detects the clock start, and the scope shows the transition from CLK LP -> CLK HS.
Questions:
1) Is there a required time delay between MIPI D-PHY power-up and CSI Tx power-up to ensure proper clock signal transitions?
2) Could you please help us understand why this issue becomes visible at lower temperatures?
3) We have performed the following ADI-recommended writes after MIPI D-PHY power-up:
CSI MAP D2 0xF7
CSI MAP D8 0x65
CSI MAP E0 0x09
CSI MAP 2C 0x00
Unfortunately, the "ADV7281 Hardware Reference Manual UG-637" does not provide details on these registers. Could you provide information on their purpose and functionality?
