Alternating black and red pixel on the vertical line

Hi,

Kindly note that Progressive MIPI output is only available on the ADV7280-M and ADV7282-M models, but you were using the ADV7281-M part.

The advanced interlaced-to-progressive (I2P) function allows the 'ADV7280, ADV7280-M, ADV7282, ADV7282-M and ADV7283' to convert an interlaced video input into a progressive video output.

Thanks,

Poornima

Hello Poornima Subramani,

Thank you for your reply!

As we do deinterlacing in the remaining part of the video-in pipeline. However, even if we collect one-field frames and deinterlace manually, the resulting video is the same.

The problem here is that we observed "Alternating black and red pixels vertically" on the one-field frame captured from ADV, which suggests that maybe the issue originates from the ADV7281-m.

Regards,

Vinh

Hi,

   As stated in previous reply, ADV7281-M part doesn't support I2P functionality.

  Please confirm whether you are observing the same issue even without I2P ?

Thanks,

Poornima

PoornimaSubramani said:

  Please confirm whether you are observing the same issue even without I2P ?

Hi Poornima, Yes, the issue persists on one-field frame (odd/even frames) (without I2P).

Thanks,

Vinh

Hi,

If Possible, Please share your register configuration.

Please make sure whether ADV728x is programmed correctly with ADI recommended I2C writes,
Also make sure the power rails to the ADV728x are clean and stable

Please ensure with good ground connections on the board i.e ground plane.
Also try disabling the PLL (Register 0x00[1]) and see if this reduces flicker. If it does, your PVDD supply has noise on it.
If the issue disappears with the PLL disabled is a good indicator that the problem lies in the external loop filter circuitry. The external loop filter circuit is extremely sensitive and connecting it to an unfiltered supply will most likely in all cases lead to poor performance.
Any noise on the external loop filter circuit supply can cause a poor performance.
Please crosscheck your schematic with reference one and follow the basic circuits and layouts as per reference designs.

Note: "ADI recommended Write" - if those writes are not included, the part would not work reliably (unless those values are default anyway). Those registers are generally internal settings that let us handle process variation which is why they are determined during characterization. The settings that show up as "ADI Recommended Settings" are the values that work reliably across voltage and temperature. They really should be called "ADI Required setting.
In these applications note AN-1337 at AN-1337 with covers most of the issues that customers encounter when interfacing the ADV728x-M family of parts with MIPI receivers.

Thanks,

Poornima

Hello Poornima, 

Sorry for the late reply, and thank you very much for your hints!

However, I couldn’t find the PLL register settings, to be honest. According to the ADV hardware manual [1], the register address 0x00 is for input control. Could you please specify the page where the PLL register settings are located?

Currently, I’m adding some logs to capture all of our ADV7281-M settings while requesting the tester to run our use case. I would also like to try disabling the PLL, as you suggested. I also observed that the “ADI Recommended Write” is configured as follows:

[1] https://www.analog.com/media/en/technical-documentation/user-guides/adv7280_7281_7282_7283_ug-637.pdf

Thank you for your support!

Vinh

Hi,

  Please let us know your DAC part and there we have the register for disabling the PLL.

Thanks,

Poornima 

Hello Poornima,

From my understanding is that this DAC ("Digital to Analog Converter") part is from our "Video source ECU." Unfortunately, it is provided by our third party, and it is a black box for us.

Thanks

Vinh

Hi,

  If DAC is a black box in your case, Please check the PLL power supply(PVDD) since PVDD is very important for maintaining the video stability.  Ideally it should be ferrite bead isolated from other supplies.

All power rails can affect the output images and PVDD is most sensitive to noise. So first check PVDD noise both high frequency and lower frequency around the horizontal rates.  If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

Also during power-up, could you check the power supplies, reset and powerdown pins using an oscilloscope. Just to double check that the optimal power-up sequence is followed. You can also check if noise is present on the supplies (The PVDD and AVDD are the most sensitive to noise).

Kindly note that, By default the ADV728x outputs in a BT.656-3 format. For example if the receiver is expecting ITU-R BT.656-4 but ITU-R BT.656-3 is being output from the ADV728x then this can cause abnormal result in the screen, So could you please try toggling the BT656-4 bit (User Map, Register 0x04 bit [7]).

When the BT.656-4 bit equals to 0 (default), the ADV728x-T outputs video that is compatible with the ITU-R BT.656-3 standard. When the BT.656-4 bit equals 1, the ADV728x-T outputs video that is compatible with the ITU-R BT.656-4 standard.

Please check with below register and let us know the result,

Thanks,

Poornima

Hello Poornima,

As I have tried with ITU-R BT.656-3/-4 standard as the script bellow:

init_device - init_device
adv7281_set_power_pin - adv7281_set_power_pin
adv7281_write - ADV7281 write: page:0, reg=0x000f, val=0x04
adv7281_write - ADV7281 write: page:0, reg=0x000f, val=0x80
adv7281_init - adv7281_init
adv7281_write - ADV7281 write: page:0, reg=0x00fe, val=0x88
adv7281_init - ADI recommended writes for improved video quality
adv7281_write - ADV7281 write: page:0, reg=0x0080, val=0x51
adv7281_write - ADV7281 write: page:0, reg=0x0081, val=0x51
adv7281_write - ADV7281 write: page:0, reg=0x0082, val=0x68
adv7281_init - ADI required writes
adv7281_write - ADV7281 write: page:0, reg=0x0003, val=0x4e
adv7281_write - ADV7281 write: page:0, reg=0x0004, val=0x57
adv7281_write - ADV7281 write: page:0, reg=0x001d, val=0xc0
adv7281_write - ADV7281 write: page:0, reg=0x0013, val=0x00
adv7281_set_power - adv7281_set_power
adv7281_write - ADV7281 write: page:0, reg=0x000f, val=0x04
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x00de, val=0x02
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x00d2, val=0xf7
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x00d8, val=0x65
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x00e0, val=0x09
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x002c, val=0x00
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x001f, val=0xc0
adv7281_set_bt656 - adv7281_set_bt656
adv7281_write - ADV7281 write: page:0, reg=0x0004, val=0xd7
adv7281_select_input - adv7281_select_input
adv7281_write - ADV7281 write: page:0, reg=0x0000, val=0x0e
adv7281_write - ADV7281 write: page:128, reg=0x809c, val=0x00
adv7281_write - ADV7281 write: page:128, reg=0x809c, val=0xff
adv7281_write - ADV7281 write: page:0, reg=0x0017, val=0x41
adv7281_write - ADV7281 write: page:0, reg=0x0052, val=0xc0
adv7281_write - ADV7281 write: page:0, reg=0x0053, val=0x4e
adv7281_write - ADV7281 write: page:0, reg=0x0054, val=0x80
adv7281_write - ADV7281 write: page:0, reg=0x005f, val=0xa8
adv7281_write - ADV7281 write: page:0, reg=0x005a, val=0x90
adv7281_write - ADV7281 write: page:0, reg=0x0060, val=0xb0
adv7281_write - ADV7281 write: page:128, reg=0x80b6, val=0x08
adv7281_write - ADV7281 write: page:128, reg=0x80c0, val=0xa0
adv7281_write - ADV7281 write: page:0, reg=0x0031, val=0x02
adv7281_write - ADV7281 write: page:0, reg=0x0051, val=0xa4
init_device - Optimize ACE Performce
adv7281_write - ADV7281 write: page:64, reg=0x4084, val=0x00
adv7281_write - ADV7281 write: page:64, reg=0x4080, val=0x80
adv7281_write - ADV7281 write: page:32, reg=0x2040, val=0xd1
adv7281_write - ADV7281 write: page:32, reg=0x2044, val=0x03
adv7281_write - ADV7281 write: page:32, reg=0x2048, val=0x00
adv7281_write - ADV7281 write: page:32, reg=0x204c, val=0x0a
adv7281_write - ADV7281 write: page:32, reg=0x2050, val=0x00
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x00
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x00
adv7281 1-0021: Registered irq 210
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x02
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x00
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x01
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x00
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x00
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x08
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x02
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x00
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x01
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x00
update_lock_status - update_lock_status
adv7281_write - ADV7281 write: page:32, reg=0x2043, val=0x00
adv7281_write - ADV7281 write: page:32, reg=0x204b, val=0x02

adv7281_s_stream - adv7281_s_stream
adv7281_csi_write - CSI: write: client.addr=0x0044, reg=0x0000, val=0x00