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Request for Schematic Review – ADV7280BCPZ Circuit

Thread Summary

The user requests a review of their ADV7280BCPZ schematic for CVBS to BT.656 video conversion, focusing on input termination, I2C connections, clock design, power supply decoupling, and output routing. The final answer provides links to detailed resources on crystal and clock configurations, emphasizes grounding the exposed pad, maintaining a solid ground plane, and ensuring clean PVDD_1V8 supply. It also advises on minimizing trace lengths for analog inputs and selecting appropriate resistor values (75 Ω for pseudo differential, 150 Ω for fully differential CVBS inputs).
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Category: Hardware
Product Number: ADV7280BCPZ, ADV7280

A-100_R04_250711.zip

Dear ADI Support Team,

We are currently working on a design based on the ADV7280BCPZ video decoder. To ensure that our schematic implementation aligns with Analog Devices’ best practices, we would like to request your support in reviewing the attached circuit design file.

Part Number: ADV7280BCPZ 
Application: CVBS to BT.656 Video Conversion 


 Requested Review Scope:
1. Input section (CVBS termination and AC coupling)
2. I2C interface connections
3. Clock and crystal design
4. Power supply and decoupling
5. Output format and LLC routing

We’ve attached our current schematic in the form of a *.DSN file (OrCAD design).
Filename: A-100_R04_250711.DSN

Please let us know if there are any issues or recommended changes. We aim to complete this design soon, so your timely feedback would be greatly appreciated.

Parents
  • Hi,

        Please refer to the threads below to get the details about the crystal, clock, and hardware connections.

     How Do I Use an External Oscillator to Clock the ADV728x ? 

     Explanation As To Why the Crystal Does Not Oscillate on ADV7182 or ADV728x Systems After Powerup 

     How to get Crystal Clock output on GPIO pin of ADV728x 

     How to Detect That the Crystal is Working Correctly on the ADV7182/ADV728x 

       Regarding hardware connections,

    1. Please check exposed pad is to be tied to ground since many people miss this.

    2. Keep a solid ground under the part

    3. Keep PVDD_1V8 very clean since PVDD is very important maintaining video stability.

        Ideally it should be ferrite bead isolated from other supplies. The data sheet reference schematic does not show this which is OK if the PVDD source is very clean. Unfortunately I do not have acceptable hard noise figures to give you.

        First check PVDD noise both high frequency and lower frequencies around the horizontal rates. If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

        Also when routing the analog interface inputs on the PCB, keep track lengths to a minimum. Use 75 Ω trace impedances when possible; trace impedances other than 75 Ω increase the chance of reflections. The divider network traces will then be very short and have effect on reflection.

        Please select the resistor R1 value according to your input.
        For a pseudo differential CVBS input, a value of 75 Ω is recommended for R1.
        For a fully differential CVBS input, a value of 150 Ω is recommended for R1.

        Expert created a simple tool PCB Trace Impedance Calculator  for impedance calculations.  You should use your layout tool for better results.  For 75 Ohm board would came up with 5 mil width, 1.4 mil thickness, 7 mil prepreg giving 75 Ohm impedance PCB.  spacing of 10 mils gets Zd = 131 Ohm.  

    Thanks,

    Poornima 

Reply
  • Hi,

        Please refer to the threads below to get the details about the crystal, clock, and hardware connections.

     How Do I Use an External Oscillator to Clock the ADV728x ? 

     Explanation As To Why the Crystal Does Not Oscillate on ADV7182 or ADV728x Systems After Powerup 

     How to get Crystal Clock output on GPIO pin of ADV728x 

     How to Detect That the Crystal is Working Correctly on the ADV7182/ADV728x 

       Regarding hardware connections,

    1. Please check exposed pad is to be tied to ground since many people miss this.

    2. Keep a solid ground under the part

    3. Keep PVDD_1V8 very clean since PVDD is very important maintaining video stability.

        Ideally it should be ferrite bead isolated from other supplies. The data sheet reference schematic does not show this which is OK if the PVDD source is very clean. Unfortunately I do not have acceptable hard noise figures to give you.

        First check PVDD noise both high frequency and lower frequencies around the horizontal rates. If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

        Also when routing the analog interface inputs on the PCB, keep track lengths to a minimum. Use 75 Ω trace impedances when possible; trace impedances other than 75 Ω increase the chance of reflections. The divider network traces will then be very short and have effect on reflection.

        Please select the resistor R1 value according to your input.
        For a pseudo differential CVBS input, a value of 75 Ω is recommended for R1.
        For a fully differential CVBS input, a value of 150 Ω is recommended for R1.

        Expert created a simple tool PCB Trace Impedance Calculator  for impedance calculations.  You should use your layout tool for better results.  For 75 Ohm board would came up with 5 mil width, 1.4 mil thickness, 7 mil prepreg giving 75 Ohm impedance PCB.  spacing of 10 mils gets Zd = 131 Ohm.  

    Thanks,

    Poornima 

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