Problem with ADV7280A power

Hi,

  Generally, VDD_IO can be operated at either 1.8V or 3.3V. When operating at 3.3V,the voltage limits are between 2.97 V to 3.63 V and when operating at 1.8V the voltage limits are between 1.71V to 1.89V. This is how the datasheet specifies.

  Kindly note that, When VDD_IO is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should be 1.8V levels. Vdd_IO and Vaa are nominally 3.3V rails while Vdd and PVdd are 1.8V rails.

  When the ADV7281 operates with a nominal DVDDIO voltage of 1.8 V, then the drive strength of all digital outputs must be set to maximum.
  Note that when DVDDIO is 1.8 V, no pin of the ADV7281 should be pulled up to 3.3 V. For example, the I2C pins of the ADV7281 (SCLK and SDATA) should also be pulled up to 1.8 V instead of 3.3 V.

  As per expert comment, In general for all ICs absolute maximum ratings are dependent on

• Gate oxide breakdown threshold
• ESD protection activation limits
• Thermal limitations

Also Please let us know, What the statement means "there is no problem when there is no ADV7280A on the chip so the 1.8v power has no problem itself" 

Thanks,

Poornima

Hi again and thanks for your reply. I mean when the chip is not soldered, 1.8v power supply is ok, but the chip is soldered, I see the 1.8v power of the boards goes to 2.4v. In my design, DVDDIO is connected to 3.3v and all other power pins are connected to 1.8v. 

Hi,

 As per expert comment, We could power up 3.3V and never power up 1.8V and this should not damage the part.

 Could try putting some resistive load on the 1.8 rail (i.e ~100 Ohms) and let us know.

 Kindly refer our expert response at  RE: POWER-UP SEQUENCE of ADV7611 

Thanks,

Poornima

Hi Dears,
I put a 100ohm load on the 1.8 rail and my problem with the 1.8 power solved. I don't know why ! Thank you very much.
Now I am working with the chip and have problem with testing free-run mode. Is there a document(except that script) to know which packets should I send via I2C to test different modes?

best regards

Hi,

  Please refer free run operation section at ADV7281/ADV7281-M / ADV7281-MA Design Support Files - Documents - Video - EngineerZone

  Also refer this FAQ at FREE RUN - Documents - Video - EngineerZone

Thanks,

Poornima

Hello dear,
Sorry for asking too many questions!
I’ve been trying to set up the Free Run mode for a while, but I still haven’t succeeded. With the following configuration, there is no signal on the crystal pins, and neither HSync nor VSync work correctly(I observe irregular signals with no specific frequency on these pins)

42 0F 80 ; Reset ADV7280A
delay 10 ; Wait 10ms
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver [ADV7280A writes finished]

I have 2 questions about this config:
register 0x13 is a status and read only register according to the datasheet, why here we have this?
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal   

and there is no registers with 0x80,0x81,0x82, So what are there in the config script for theses registers?

best regards

Hi,

   Freerun should work, Kindly force other standard instead NTSC using register '0x02'  and let us know.

   Please refer below response for your questions,

Register 0x13 is a status and read only register according to the datasheet, why here we have this?
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal   

          Please refer below expert comment regarding '0x13' register, 

          Both a read and a write register share the address 0x13. The write register is currently not documented. I will add a description of this register in the next revision of the ADV728x hardware manual.

Please write 0x00 to register 0x13 if you are using a 28.63636MHz crystal to clock the ADV728x.

Please write 0x02 to register 0x13 if you are using a 28.63636MHz oscillator to clock the ADV728x.

This register has been discussed in the thread https://ez.analog.com/message/80298#80298

There is no registers with 0x80,0x81,0x82, So what are there in the config script for theses registers?

    These registers corresponds to ADI required write and these writes are normally determined during characterization of the part and we typically do not release any detail on them unfortunately.

     Kindly note that, If those writes are not included, I would not expect the part to work reliably. Those registers are generally internal settings that let us handle process variation which is why they are determined during characterization. The settings that show up as "ADI Recommended Settings" are the values that work reliably across voltage and temperature. They really should be called "ADI Required settings at ADI Recommended Setting 

    Please refer  register settings 

Thanks,

Poornima

Thank you for your quick response. Changing the  register '0x02' did not make any difference.
My question is that it seems the crystal is still not working.
Is it actually possible to observe the crystal output using an oscilloscope?

I followed the method described in the link below, and according to that link the crystal is working correctly, but nothing can be seen on the oscilloscope, and the Hsync,Vsync still have  irregular frequency.

How to Detect That the Crystal is Working Correctly on the ADV7182/ADV728x

this is my Crystal Circuit

For more details:
I want to have a PAL input and Parallel output from ADV7280A and then Parallel video goes to a second chip with HSync,VSync and LCC. Now the second chip is not assembled on my board and I want just to run and test "free run mode" first on ADV780A. I expect to see the HSync and VSync correctly(but I have not seen yet!) .
I use this script:

delay 10 ; Wait 10ms After Hardware Reset To Start I2C
42 0F 80 ; Reset ADV7280A
delay 10 ; Wait 10ms
42 0F 00 ; Exit Power Down Mode [ADV7280A writes begin]
42 52 CD ; AFE IBIAS
42 00 07 ; ADI Required Write [INSEL set to unconnected input]
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 17 41 ; Enable SH1
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads(also I testes 0x3F for this)
42 13 00 ; Enable ADV7280A for 28_63636MHz crystal
42 1D 40 ; Enable LLC output driver

this is HSync that I see:

Hi,

 Please make sure the crystal is as specified in the datasheet in regards to the load capacitance. If the load capacitance is different then C1 and C2 can be re-calculated.

  Refer 'ADV7181C_Manual_RevC.pdf' at Page 263, It has a section on "XTAL and Load Cap value Selection". 

 Did you perform a 'heartbeat' test ? In order to determine the crystal connected to the ADV7182/ADV728x is oscillating. The heartbeat test works by setting and clearing an interrupt bit. If the crystal is not oscillating correctly then the interrupt will not be set and cleared correctly.

 Also Kindly ensure with below things,

  -- Do NOT place a resister between XTAL pins of the ADV728x.
  -- The ADV728x contains a large internal resistance between the XTALP and XTALN pins. The addition of another external resistor in parallel, causes the overall resistance between the pins to decrease.
  -- This makes it harder for the ADV728x to start the crystal oscillating (i.e This will make it harder for the crystal to start oscillating at some PVT corners).
 -- Some crystal manufacturers advise placing a small capacitor (1pF - 2pF) between the crystal pins in order to achieve stable oscillation.

Thanks,

Poornima

Thanks 

I again tell this:
Heartbeat test is ok, but I do not see anything with oscilloscope. Is it ok? If yes, Why there is an irregular frequency on HSYNC?
note: the picture of the circuit is attached to the last message.
regards