Product Number: ADV7280A-M
Environment
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Platform: Linux kernel-based embedded system (i.MX)
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Interface: MIPI-CSI-2
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Driver: Standard ADV7180 Linux kernel driver implementation (https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/drivers/media/i2c/adv7180.c)
Issue Description
We're experiencing image quality degradation when frequently cycling the power state of the ADV7280A-M decoder. After debugging the kernel driver, we discovered that our application's stream-on/stream-off operations trigger a repetitive power cycling sequence (power-on → stream-on → stream-off → power-down).
With our application performing these cycles extensively, the camera image eventually exhibits various anomalies:
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Color distortion
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Image darkening
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Black and white image instead of color
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Other color space inconsistencies
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The power management register (0x0F) is being accessed as follows in the kernel driver:
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Power ON: Writing 0x04 to register 0x0F (PWRDWN bit = 0)
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Power DOWN: Writing 0x24 to register 0x0F (PWRDWN bit = 1)
These operations can be traced in the Linux kernel implementation here:
https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/drivers/media/i2c/adv7180.c#L516-L546
Workaround
We've implemented a delayed power-off mechanism in our driver that only powers down the device if no power-on operations are requested within a configurable time window. This approach has fixed the issue in our testing.
Questions
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What are the possible implications of setting the power down bit multiple times that could affect image quality?
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Is the issue related specifically to the PWRDWN bit transitions (1 or 0), or could it be caused by other register settings that make the PWRDWN operations problematic?
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Are there recommended practices for managing power states when applications require frequent stream cycling?
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Is there a specified minimum time that should be maintained between power-down and subsequent power-up operations?
Thank you for your assistance.
The decoder
[edited by: Veethree at 8:37 AM (GMT -4) on 9 Apr 2025]
