ADV7280A-M Registers Questions

Hi,

  Regarding powerup issue, Please follow the optimal power-up sequence described in the datasheet is how the ADV728x is powered up during in-house testing. It is the safest method of powering up the ADV728x part. Please refer below snap,

Also ensure the below mentioned point when programming the ADV728x.

- Apply power supply as required
- Wait for 5 millisecond (ms) period
- Apply a reset for 5 ms period
- Wait 5 ms after reset has been de-asserted
- Program the ADV728x as advised on our I2C script

Kindly note that, Regarding register questions we don't have any register related details other than what available in the ADV728x manuals.

Thanks,

Poornima

Unfortunately on my prototype board there is no way of sequencing the supplies, both the 3V3 and 1V8 come up at the same time. I did note that 1V8 does not exceed 3V3 during this period. I will keep this in mind for the production release, thank you.

"Kindly note that, Regarding register questions we don't have any register related details other than what available in the ADV728x manuals."

Not what I expected to hear. How were the registers and values in the script determined then? This doesn't fill me with a lot of confidence.

Hi,

  Script configuration been made by referring the same family chipset manuals since 'ADV718x/ADV728x' related parts will come under same family. 

Thanks,

Poornima

Hi Poornima

Think we are having a similar issue in that each time we stop and then restart video, and therefore toggle the 0x0F PWRDWN bit, there is a chance of it coming back with blue and red swapped, or no colour, or very dark, or wavy vertical bars where blue and red swap. And once in that state, it is generally stuck in that state, even after more PWRDWN cycles. Never setting PWRDWN to 1 works around the issue, but is obviously a hack?

Not sure if the issue is the PWRDWN itself, or the powering back up, or some other register settings that take effect at that time?

I have also tried masking the bits when writing to 0x03 and 0x04 as Chris suggested (read/mask/write), but unfortunately that alone didn't seem to fix the issue for us.

In the script from Customer Version 5.0 August 2017 ADV7280A-M

:I2P AUTODETECT CVBS Single Ended In Ain 1, 480p/576p MIPI Out:
...
42 03 4E ; Power down unused pads
42 04 57 ; Power-up INTRQ pin

0x57 is 0101 0111

which means for address 0x04:
Bit 7: default 0, new 0, unchanged, ITU-R BT.656-3 compatible
Bit 6-4: default 011, new 101, changed, Reserved / undocumented
Bit 3: default 0, new 0, unchanged, TIM_OE
Bit 2: default 1, new 1, unchanged, BL_C_VBI
Bit 1: default 0, new 1, changed, EN_SFL_PIN
Bit 0: default 1, new 1, unchanged, Extended range

The script says Power-up INTRQ pin.
But the manual does not refer to any of those bits as INTRQ pin?
Or at least not that section?

And as Chris asked, is it not strange that the script changes the Reserved bits from the default 011 to 101?

Thank you
-- Peter

Hi,

Please find the below comment,

1). The script says Power-up INTRQ pin.
But the manual does not refer to any of those bits as INTRQ pin?
Or at least not that section?

Please refer below expert comment about 0x04 register description about INTRQ Pin

     The ADV728x die contains two INTRQ pads. Only one of these is bonded out on the ADV7282-M. By setting these bits to 0b'101 ensures that the correct INTRQ pad is selected So user map register 0x04 bits [6:4] do need to be set to 0b'101. 

     This description to be added in the next revision of the ADV728x hardware manual.

2). Also try to configure 0x03 as 42 03 0C ; Enable Pixel & Sync output drivers.