7604 VSYNC pulse width

Hi,

  If Possible, Please share your register configuration.

  Also monitor the 'V_LOCKED_RAW, V_LOCKED_ST, TMDS_LCK_x_RAW' during that case and also ensure the recommended writes as per this document "ADV7604_RecommendedSettings_Rev2.5.pdf"

  Generally, format changes can cause V_LOCK to unlock it may take a frame or 2 for the chip to lock on to the new format. During this interval you can either free run or black screen the video.

Please check with other source device since some source may not generate a Stable VSYNC Signal during resolution change

Thanks,

Poornima

Hi,

here is our register configuration:

;AD7604
40 0C 42 ; Power up part and power down VDP
40 00 07 ; VID_STD=00111b for autographics mode
40 15 BE ; Tristate all outputs from video core
68 1A 1A ; Mute audio
68 01 78 ; Open termination
40 F7 66 ; DPP Address to 66
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 12 ; RGB 0-255 out, Set ALT_DATA_SAT --- EZ ---
40 03 40 ; 24 bit SDR 444 Mode 0 
40 05 28 ; AV Codes Off, blank data
40 06 A1 ; Inv LLC 
40 0B 44 ; Power down ESDP block
40 14 7F ; Drive strength adjustment
40 15 80 ; Disable Tristate of Pins
40 33 60 ; LLC DLL Mux Enable
44 69 00 ; Disable CP CSC --- EZ ---
44 6C D0 ; CLMP_A_MAN and CLMP_BC_MAN set to 0 --- EZ ---
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use seperate HS & VS.
44 BA 00 ; HDMI FreeRun disable
44 CF 01 ; Power off macrovision
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer/bandgap/clamps/sync strippers/input mux/output buffer
4C 13 93 ; Set LLC DLL Phase
4C B5 01 ; Setting MCLK to 256Fs
4C C8 40 ; ADI recommended setting
68 01 00 ; Enable clock terminators
68 0D 84 ; ADI recommended write
68 15 03 ; Set Audio FIFO Mute Masks
68 1A 0A ; Set Unmute Delay to 1_5 sec
68 3D 10 ; ADI Recommended Setting
68 3E 39 ; ADI recommended setting
68 48 06 ; Set Audio FIFO reset
68 57 B6 ; Enable dynamic PLL control
68 58 03 ; Recommended PLL setting
68 59 A3 ; ADI recommended setting
68 8C A3 ; ....dflt.....
68 8D 18 ; ADI recommended equalizer setting.
68 8E 34 ; ADI recommended equalizer setting
68 93 8B ; Equaliser ADI recommended setting
68 94 2D ; Equaliser ADI recommended setting
68 96 01 ; Enable automatic EQ changing

V_LOCKED_RAW and TMDS_CLK_x_RAW indicate locked state (1) when VSYNC is not standard ("error" state). What is the meaning of V_LOCKED_ST?

Thanks

Vilem

Hi,

   Please let us know the reason for tristate(high impedance) the "Pixel bus / LLC Pin / Sync out Pins" (i.e 40 15 BE).

   Also its seems, the 'VID_STD' register has not been configured to graphics mode (40 00 07 ; VID_STD=00111b for autographic mode) and let us know your graphic mode resolution.

V_LOCKED_ST - Latched status for the vertical sync filter locked interrupt. Once set, this bit will remain high until the interrupt is cleared via V_LOCKED_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.

Kindly note that, "_ST is the latched  version of _RAW " _CLEAR clears the _ST bit. 

                             ST bit is the latched version of RAW so RAW could be low while ST is high.

Thanks,

Poornima

Hi,

yes, you are right, there is no reason for 40 15 BE, because BE is default value and there is no reason why to  write it. On the row nr. 14 there is 40 15 80 write for disable tristate of pins. 

Why do you think the VID_STD has not been configured to autographics mode? It was the only way how to make 7604 operational with 1024x2048 resolution. We solved in with ADI support on Apr 17 2024.

Thank you for explanation of V_LOCKED_ST.

Thanks

Vilem

Hi,

  Please let us know, In which manual are you referring to configure the 'VID_STD' register ?

Thanks,

Poornima

Hi,

here is a part of communication that was carried approx. 1 year ago:

Hi,

Hi,

  Please find ADV7604 hardware manual here /cfs-file/__key/communityserver-discussions-components-files/331/ADV7604-HW-RvF-Aug_2700_10.pdf

   At first please check the graphic mode resolution which is available in the 'VID_STD' register(Refer Page 49) and let us know the result.

Thanks,

Poornima

Hi,

I tested two configurations:

1. PRIM_MODE=0x6 (0b0110) - HDMI-GR; VID_STD[3:0]=0b00111 (reserved) - autographics ?

2. PRIM_MODE=0x6 (0b0110) - HDMI-GR; VID_STD[3:0]=0b00110 (1280x1024/75Hz)

It seems both configurations work with our 1024x2048/60Hz. Is really autographics mode available for DVI/HDMI input? 

Thanks

Vilem 

Hi,

  Yes, Autographic mode is available for both DVI/HDMI input.

  Please refer DVI script configuration at ez.analog.com/.../6114.ADV7604IO_5F00_ADV7604CP_5F00_ADV7604AFE_5F00_ADV7604HDMI_5F00_ADV7341B_2D00_VER.1.4c_5F00_RevA.txt.zip

Thanks,

Poornima

Hi,

unfortunately, I don´t understand. One of two notices about autographic mode is for example here:

##Graphics - UXGA, 1600x1200##
:Graphics-8.2 1600x1200 _@ 60 162.000MHz Out through DVI:
50 20 10 ; FPGA HPD on TX
40 0C 42 ; Power up part and Power down VDP
40 00 16 ; VID_STD=00111b for autographics mode

......

But for aotographics mode there should be 40 00 07 and not 40 00 16.......??

By the way, what about original topic - the width of VSYNC signal? This still sometimes appears and the graphics mode has no influence on it.

Thanks

Vilem