ADV7613
Recommended for New Designs
The ADV7613 is a high quality, low power, single-input HDMI
to LVDS display bridge. It incorporates an HDMI capable
receiver that supports up to 1080p...
Datasheet
ADV7613 on Analog.com
Hi
Please find response below for the query asked.
1. Review PCB layout: Ensure differential pair routing, Short Trace length, Impedance matching, and Good Grounding.
These points have been reviewed and checked.
2. Check LVDS termination: Make sure proper termination is in place for both driver and receiver. LVDS termination 100E at Display side. For HDMI the termination is inside the IC
3. Verify voltage levels: Ensure correct voltage levels for the LVDS signals
All LVDS data signals + clock signals have the same voltage levels and frequency also matching
4. Check clock settings: Confirm the pixel clock frequency and external clock stability.
Pixel clock frequency is 65MHz and external clock is stable
5. Check output format: Ensure the output format is correctly configured.
Could you please clarity on output format that we have to check. Do you mean LVDS output configuration? We have configured LVDS output as a 6-bit openLDI bitmapping, which is asper LCD display that we are using.
6. Ensure proper grounding and shielding: Minimize EMI and signal noise.
It is a multilayer board with proper stackup and GND plane. The unshielded local board works properly, so shielding should not be a problem.
Response for the PCB Layout and Trace Integrity,
1. Trace Impedance Matching: LVDS signals require controlled impedance traces. Ensure that the PCB layout follows this rule and that the LVDS traces are well-matched in terms of impedance.
100E differential impedance maintained
2. Short Trace Lengths: Keep the LVDS signal traces as short as possible to reduce signal degradation and minimize noise pick-up.
100-ohm differential impedance is typically 2-4 inches (5-10 cm), but can be longer depending on data rate, in our board the track length is about 2” or less.
3. Differential Pair Routing: Ensure that the LVDS differential pairs are routed close together to maintain good signal integrity. Ideally, the traces should be routed on the same layer with minimal spacing to preserve the differential signal.
Similar to first point. This is ensured.
4. Ground Plane: Use a solid, uninterrupted ground plane beneath the LVDS traces to provide a low resistance return path for the differential signal and reduce the chances of noise and distortion.
Refer to my response for point 6 above.
We have checked on to these cases and here are the results
1. Try the LVDS output at Port B - "02-02 HDMI Input_LVDS Output Port B" We have probed on to the LVDS output on Port B , here the OpenLDI BITMAPPING WITH 6-BIT COLOR DEPTH is the configuration , so the output are three data lanes
2. Check when Dual LVDS port is enabled - "02-03 HDMI Input_LVDS Output Port A and B"
This testing cannot be done on the customised board . Here ADV7613 LVDS output either be configured on Port A or Port B
3. Back-to-Back / Direct Connection (Source --> Sink)
Checked
4. Change source and sink device and also cable.
Checked
I am attaching the image of the LCD screen. The screen is still having distorted image. From the source device we have ran notepad application to be displayed on LCD screen.
Questions
1.In the script :02-02 HDMI Input_LVDS Output Port B: it's mentioned to write C0 4E 34 for port B selection.
But asper reference manual of ADV7613, it's mentioned to write C0 4E 24 for port B selection.
Could you please clarify on port selection.
2. AKSV_UPDATE_A_RAW is 0, it indicates that the transmitter has not written its AKSV into the HDCP registers for Port A. Do we have to consider this condition, as we are processing unencrypted data.
Please let me know if any information is needed from our end.
Thanks
Neelima S
Hi,
For Port B, Reference script(C0 4E 34) configuration is the correct/right configuration for Port B selection.
Please let us know, Where it is mentioned in ADV7613 reference manual to write C0 4E 24 for port B selection.
Please find below comment for your query,
Could you please clarity on output format that we have to check. Do you mean LVDS output configuration? We have configured LVDS output as a 6-bit openLDI bitmapping, which is as per LCD display that we are using ?
As per your 6-bit LCD display, you need to configure 0x4C as "C0 4C 10". Please refer below snap,
Kindly note that, there is no dithering block available for the LVDS transmitter output when outputting Six bits per color component. If required,
dithering must be done externally.
AKSV_UPDATE_A_RAW is 0, it indicates that the transmitter has not written its AKSV into the HDCP registers for Port A. Do we have to consider this condition, as we are processing unencrypted data.
No Need to consider the HDCP related registers since it is unencrypted data.
Thanks,
Poornima
Hi
Questions:
In the script :02-02 HDMI Input_LVDS Output Port B: it's mentioned to write C0 4E 34 for port B selection.
But asper reference manual of ADV7613, it's mentioned to write C0 4E 24 for port B selection.
Could you please clarify on port selection.
Thanks
Neelima S
Hi Poornima
From above snap, we can analyse to select Port 2, we need to set TX_BYPASS_PIX _DEMUX to 1 and TX_PIXEL_SWAP to 0. Therefore, C0 4E 24 as the value to write to select Port 2.
Thanks
Neelima S
Hi,
Please follow as per latest Rev A (UG-907) document since script configuration might have been made according to the Rev 0 (UG-898) document. Refer below snap for reference
Kindly refer this (ADV7613)UG-907 Rev0 vs RevA - Q&A - Video - EngineerZone
Thanks,
Poornima
Hi,
Below are the only section which are modified from 'Rev 0 to Rev A' UG So while configuring we need to take care these registers according to latest 'Rev A' document but rest of the script configuration remains same.
Kindly note that, we don't have any files or document other than what available in the design support and product page of ADV7613 part.
Thanks,
Poornima
Hi Poornima,
Thank you .
We have encountered an issue with the Standard Detection and Identification (STDI) block configuration. According to the ADV7613 documentation, there are three operational modes for the STDI block:
We have configured the STDI block in both continuous and single-shot modes.
1)However, when checking the CH1_STDI_CONT and the data valid flag (CH1_STDI_DVALID), the flag indicates that the measurements are not valid.
Additionally, the readback values for block length, line count, line count in a field, and field length do not match any values provided in the STDI readback values for GR.
The screen displays a mix of grey and white when trying single shot and continuous modes.
Here is a summary of my configuration steps:
Set CH1_STDI_CONT to 0 for single-shot mode. Start the measurement by setting CH1_TRIG_STDI flag and clear the flag by writing 0 to it.
Set CH1_STDI_CONT to 1 for continuous mode.
Checked the CH1_STDI_DVALID flag, which remains low.
Read back the values for block length, line count, line count in a field, and field length, which do not match expected values.
44 B1 3F
44 B2 FF
44 B3 00
44 A3 00
44 A4 00
44 B8 06
44 B9 94
Could you provide me with the correct configurations?
2) Configured the free run mode by enabling HDMI_FRUN_EN and setting HDMI_FRUN mode to mode 0.
After this configuration, the screen colour changed from grey to light blue as shown in the image below
I am trying to understand how the free run mode impacts the screen colour and why whole screen is not blue. Do we need to remove or add any other configurations while setting up the free run mode in HDMI?
Here is a summary of my configuration steps:
Enabled HDMI_FRUN_EN.
Set HDMI_FRUN mode to mode 0.
CP_FREE_RUN is 1
3) HSD_FB readback for the measured value of HSYNC depth on Channel A is 0. Is this an expected value or do we have to configure or check any other registers?
Thanks
Neelima S
Hi,
Please configure the 'CP_FORCE_FREERUN' register for forcing the free run mode why because free run should work.
Also make sure whether your are giving proper input clock frequency (28.63636 MHz).
Thanks,
Poornima
Hi Poornima
As mentioned in our previous comments, we have set CP_FORCE_FREERUN to 1. Despite this, the screen color changed from grey to light blue.
Thanks
Neelima S
