Hi Team,
I am facing an issue with ADV7182A Evalution Script Files Registers for autodetect CVBS Analog input and getting output from video encoder ADV7341
##02_CVBS SINGLE ENDED AUTODETECT ##
: Autodetect CVBS Single Ended In Ain 1, YPbPr Out:
delay 10; Wait 10ms After Hardware Reset To Start I2C
40 0F 80; Reset ADV7182
delay 10; Wait 10ms
40 0F 00; Exit Power Down Mode [ADV7182A writes begin]
40 52 CD; SE_CVBS AFE IBIAS
40 00 00; CVBS in on AIN1
40 0E 80; ADI Required Write
40 9C 00; Reset Current Clamp Circuitry [step1]
40 9C FF; Reset Current Clamp Circuitry [step2]
40 0E 00; Enter User Sub Map
40 17 41; Enable SH1
40 03 0C; Enable Pixel & Sync output drivers
40 04 07; Power-up INTRQ, HS & VS pads
40 13 00; Enable ADV7182A for 28_63636MHz crystal
40 1D 40; Enable LLC output driver [ADV7182A writes finished]
54 17 02; Reset Encoder
54 00 1C; Power up DACs and PLL [Encoder writes begin]
54 01 00; Set Encoder to SD mode
54 80 10; SSAF Luma filter enabled, NTSC mode
54 82 C9; Step control on, pixel data valid, ped on, PbPr SSAF on, YPbPr out
54 87 20; PAL/NTSC autodetect mode enabled
54 88 00; 8-bit input enabled [Encoder Writes Finished]
End
In our project using Zynq Ultrascale Mpsoc (xczu9cg-1ffvb1156i) FPGA and need to communicate with video decoder (ADV7182A) for Analog camera as input and getting output from video encoder (ADV7341) observed camera video on monitor display. Based on these registers After Programming to FPGA the ADV7182A Registers LLC (27Mhz), Crystal (28.63636Mhz), data(P0-P7), PWRDWN and reset also working Successfully.
As part of encoder ADV7341 registers not able to display video on monitor Display. Kindly Please Support for which registers are proper working for getting video output.
Thanks
Satya
