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ADV7343 Test Pattern Issue

Hi All, We're using ADV7343 video encoder to convert 24bit RGB video to a single ended CVBS signal. For testing first we generated the test patterns as per the data sheet by successfully writing I2C data. But the LCD display at the other end does not have a sign of the video signal (nor for 24bit RGB signal). I'm pretty sure that the I2C writing and register settings are okay, specifically the following addresses loaded with the bold color values :

0x17 --> 0x02

0x00 --> 0xFC

0x82 --> 0xC9

0x84 --> 0x40

The retrieved CVBS signal from DAC4 (low drive) for the test pattern is shown below :

And the schematic we use is attached herewith. A 27MHz of clock signal is fed to the CLKIN_A of the encoder !

What could cause this issue ? I read somewhere that a termination resistor has been used to workaround a similar issue. Any suggestions would be appreciated !

Thanks in Advance

Anuradha

PS: More to this, I checked a BOSCAM with the same LCD (that's SEETEC) through CVBS. The screen displays the camera input without any issue. 

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  • Hi,

    Above you mention not being able to see the active video signal on the output of the part. What type of video signal is your host device sending? It must be 525i standard for the mode you are using. With the settings you have selected, the part should work assuming the input video signaling is correct.

    You also ask about timing information. For NTSC the front porch is typically 1.5us and the back porch is typically 0.6us. In terms of HSYNC and VSYNC timing, the following diagram for the mode you are using from the datasheet (p85) explains what is required:

    For the first case, as long as the VSYNC is low for long enough to be low when the HSYNC falls low, this should be sufficient. For the second case, as long as the VSYNC completes its transition within a HSYNC period, this should work as expected.

    Best Regards,

    Anthony

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  • Hi,

    Above you mention not being able to see the active video signal on the output of the part. What type of video signal is your host device sending? It must be 525i standard for the mode you are using. With the settings you have selected, the part should work assuming the input video signaling is correct.

    You also ask about timing information. For NTSC the front porch is typically 1.5us and the back porch is typically 0.6us. In terms of HSYNC and VSYNC timing, the following diagram for the mode you are using from the datasheet (p85) explains what is required:

    For the first case, as long as the VSYNC is low for long enough to be low when the HSYNC falls low, this should be sufficient. For the second case, as long as the VSYNC completes its transition within a HSYNC period, this should work as expected.

    Best Regards,

    Anthony

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