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ADV7343 Test Pattern Issue

Hi All, We're using ADV7343 video encoder to convert 24bit RGB video to a single ended CVBS signal. For testing first we generated the test patterns as per the data sheet by successfully writing I2C data. But the LCD display at the other end does not have a sign of the video signal (nor for 24bit RGB signal). I'm pretty sure that the I2C writing and register settings are okay, specifically the following addresses loaded with the bold color values :

0x17 --> 0x02

0x00 --> 0xFC

0x82 --> 0xC9

0x84 --> 0x40

The retrieved CVBS signal from DAC4 (low drive) for the test pattern is shown below :

And the schematic we use is attached herewith. A 27MHz of clock signal is fed to the CLKIN_A of the encoder !

What could cause this issue ? I read somewhere that a termination resistor has been used to workaround a similar issue. Any suggestions would be appreciated !

Thanks in Advance


PS: More to this, I checked a BOSCAM with the same LCD (that's SEETEC) through CVBS. The screen displays the camera input without any issue. 

  • Hi,

    Are you trying the internal test pattern?. If yes did you refer 'Internal Test Pattern Generation' Section described in the datasheet from ADV734x Design Support Files?

    Best Regards,


  • Hi Jey, Yes I am referring to the internal test pattern generation described in page 81 of the data sheet. 

  • Hi,

    What pattern and resolution are you configuring it? Whether it is SD or ED/HD

    Are you using our ADV734x evaluation board?

    The below threads  may be useful to you

    Best Regards,


  • Dear Jey,

    Hi, I found out that the issue was in the clock generation and I was able to detect the SD color bars after resolving it. Now after feeding the RGB signals from the host device, I am receiving a CVBS signal like below :


    So here, the color burst can be seen, but no color levels. Does this mean the RGB signals are not available at all ? This is my i2c writings :

    0x2B 0x17 0x02 Software reset.
    0x2B 0x00 0xFC All DACs enabled. PLL enabled (16×).
    0x2B 0x01 0x00 SD input mode.
    0x2B 0x02 0x10 RGB output enabled. RGB output sync enabled.
    0x2B 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled.
    0x2B 0x82 0xC9 Pixel data valid. RGB and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control en

    0x2B 0x87 0x80 RGB input enabled.
    0x2B 0x88 0x10 24-bit RGB input enabled
    0x2B 0x8A 0x0C Timing Mode 2 (slave). HSYNC/VSYNC synchronization.

    What causing this issue ?

  • Hi,

    Glad you got it resolved for SD color bar detection. Let me check with part specialist for the RGB signals

    Best Regards,


  • Hi Jay, can you also pls comment on the timing modes of this encoder ? So to interface this to a host machine I need to determine hback-porch hfront-porch vback-porch vfront-porch hsync-len vsync-len parameters. Do they depend on the LCD panel I interface to the CVBS out of encoder ?  

  • Hi,

    I have just forwarded this to the part specialist for his comments.

    Best Regards,


  • Thanks and for your reference, these are the timing parameters defined for the display :

    /* 800x480 @ 57 Hz , pixel clk @ 27MHz*/
    "MY-LCD", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,

    And these are the sync signals (HSYNC-Blue and VSYNC-Red) observed at the host processor RGB interface end !

  • Hi,

    Above you mention not being able to see the active video signal on the output of the part. What type of video signal is your host device sending? It must be 525i standard for the mode you are using. With the settings you have selected, the part should work assuming the input video signaling is correct.

    You also ask about timing information. For NTSC the front porch is typically 1.5us and the back porch is typically 0.6us. In terms of HSYNC and VSYNC timing, the following diagram for the mode you are using from the datasheet (p85) explains what is required:

    For the first case, as long as the VSYNC is low for long enough to be low when the HSYNC falls low, this should be sufficient. For the second case, as long as the VSYNC completes its transition within a HSYNC period, this should work as expected.

    Best Regards,


  • Dear Anthony,

    Hi, thanks for your reply. To elaborate the timing parameters, here is the generic LCD configuration entry in the host machine:

    /* 800x480 @ 57 Hz , pixel clk @ 27MHz*/
    "MY-LCD", .ref_rate=57, .hactive=800, .vactive=600, .pixel_clk=37037
    .hback-porch= 40, .hfront-porch = 60,
    .vback-porch = 10, .vfront-porch = 10,
    .hsync_len = 20, .vsync_len = 10,
    .flag = 0,},



    My intention is to get the 4bit RGB LCD display signals interfaced to this encoder and converting it to CVBS. Host machine generates a 24bit RGB signals according to the timing parameters we assign in LCD entry.

    1. So according to what you say, the timing should be compliant with NTSC standard, not the lcd parameters ? I am using a 800x480 generic lcd panel from SEETECH. 

    2. According to the datasheet, the sync signals should be in 'active low' mode, in otherwords the inverted version of the signals in the oscilloscope view right ? 

    3. Where can I find these full timing parameter list for NTSC 525i ?

    Thanks in Advance