Post Go back to editing

ADV7842

Category: Hardware
Product Number: ADV7842

We are generating a 480p output from a NTSC composite input signal in our 7842 implementation. We have it configured for interpolated deinterlacing but it appears to be falling back to line doubling mode. Every 10-20 seconds, we get a momentary jitter and it switches between doubling even fields to doubling odd fields. We get the same issue regardless of whether the 3D comb filter is turned on or off.

In addition to the user guide, I've been referring to some of the documentation for the evaluation board (see below) and have tried applying some of the recommended I2C register settings for:
1-1d CVBS NTSC_PAL-M  I_P 480p H_V_DE 24bit 422 out HDMI 

but the issue persists. 

Any idea where I can focus my efforts?

;;Reset = True;;
;;ReadInterface = True;;

Version 5.9c1
changed :DVI RGB In, RGB Out DVI:
68 00 32

Version 5.9c
To be used with FPGA mcs file version 0x50.3 or higher
Compatible with Video Output Module RevE 
For Use with ADV7842ES3 and above


----------------------------------------------------------
Revision History
----------------------------------------------------------
Version 5.9c
Added Script 9

Updated IO Map Register 0x02 writes to be one of the following.
Using limited range output to comply with CEA-861 and HDMI specs.
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 02 F6 ; Auto input color space, Limited Range RGB Output

Updated CP Gain Settings for Scripts 4 & 5. (Gain setting based on limited range output)
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8

Version 5.8c
Updated IO Map Register 0x02 writes to be one of the following:
40 02 F0 ; Auto input color space, Full Range YPbPr Output
40 02 F2 ; Auto input color space, Full Range RGB Output

Updated CP Gain Settings for Scripts 4 & 5
44 73 F2 ; Set manual gain of 0x320
44 74 0C ; Set manual gain of 0x320
44 75 83 ; Set manual gain of 0x320
44 76 20 ; Set manual gain of 0x320

Corrected write typo error in graphics scripts:
"44 C0 1F" to "4C C0 1F" 

Removed Disable of CP Pregain block write (44 3E 00) from Analog CP scripts

Removed "72 55 40 ; Set YCrCb 444 in AVinfo Frame" for RGB outputs and replaced
with "72 55 00 ; Set RGB in AVinfo Frame"

Version 5.7c
Added to Script 5-5b and 5-6b
72 3C 00 ; Disable VIC transmission from HDMI Tx

Modified to Script 5-5b, 5-6b, 6-1f, 6-2a, 6-3a, 6-4a, 6-4b, 6-4c
72 BA A0 ; Adjust clock delay

Added to SDP scripts
90 A7 00 ; ADI Recommended Write


Version 5.6c
Modified

72 3B C0 ; Disable VIC transmission from HDMI Tx for Analog non CEA-861 formats e.g. UXGA & WUXGA

Scripts 4-3g/6-1f Added write 40 33 43 ; LLC Phase Shift

Script 5-5b Added write 40 33 42 ; LLC DLL Enable

Version 5.5c
Modified
68 57 B6 ; TMDS PLL Setting
68 58 03 ; TMDS PLL Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; HDMI Recommended write
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting

Removed 68 91 & 68 8E writes
 
44 3E 00 ; Disable CP Pregain Block

44 6C 00 ; Use fixed clamp values (HDMI modes only)

Added Script 5-4c


Version 5.4c
Modified 
68 9D 02 ; ADI Equaliser Setting

Version 5.3c
Modified 
68 87 50 ; HDMI Recommended write
68 8A 1F ; ADI Equaliser Setting
68 8E 1F ; ADI Equaliser Setting
68 91 1F ; ADI Equaliser Setting
68 94 1F ; ADI Equaliser Setting


Version 5.2c
Modified 
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 93 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 87 58 ; HDMI Recommended write
68 8A 1F ; ADI Equaliser Setting
68 8E 10 ; ADI Equaliser Setting
68 91 10 ; ADI Equaliser Setting
68 94 10 ; ADI Equaliser Setting

Version 5.2c
Modified 
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 93 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 87 50 ; HDMI Recommended write
68 8A 1F ; ADI Equaliser Setting
68 8E 1F ; ADI Equaliser Setting
68 91 1F ; ADI Equaliser Setting
68 94 1F ; ADI Equaliser Setting


Version 5.1c
68 87 40 ; HDMI Recommended write

Version 5.0c

Added
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)

Changed
68 57 90 ; TMDS PLL Optimization 
68 58 01 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 85 1F ; ADI Equaliser Setting
68 8A 20 ; ADI Equaliser Setting
68 8E 20 ; ADI Equaliser Setting
68 91 20 ; ADI Equaliser Setting
68 94 20 ; ADI Equaliser Setting
68 9D 01 ; ADI Equaliser Setting


Added for ADV7511
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511


Added Writes for ADV7511
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 D1 FF ; ADI Recommended Write


Version 4.0c
Added 68 46 1F ; ADI Recommended Write ES3/Final silicon
Increased drive strength on UXGA and 1080p modes

Version 3.5c
Added several new autographics scripts to support various analog graphics inputs

Version 3.4c
Added the following autographics scripts
5-8d 1360x768@60 RGB in_ 444 24bit H_V_DE DVI
5-8e 1360x768@60 RGB in_ 444 24bit H_V_DE_DAC


Version 3.3c
Added the following settings HDMI scripts
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 57 B9 ; TMDS PLL Optimization 
68 58 63 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 98 FF ; HDMI ADI recommended write
68 99 A1 ; HDMI ADI recommended write
68 9A FF ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 8A 2A ; ADI Equaliser Setting
68 8E 2A ; ADI Equaliser Setting
68 91 2A ; ADI Equaliser Setting
68 94 2A ; ADI Equaliser Setting

4C 0C 1F ; Added to CP scripts
4C 12 63 ; Added to SDP scripts

Version 3.2c
Added additional graphics scripts

Version 3.1c 
Updated HDMI Audio scripts
- 6-2a,b, 6-3a,6-4a,b,c 
Removed 6-1g now incorporated in 6-1d 
Added 44 0C 1F ;ADI Recommended write
Removed 44 12 63 ; Default value
Added 44 C3 39 ; Added to Graphic scripts
Added 44 40 5C ; LCVS threshold adjustment
Added 68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD

Version 3.00c 
Initial ES2 Version


##Revision##
:Version 5.9c 16th November 2010 ADLK:
End


##Reset script-##
:reset:
40 FF 80 ; I2C reset
40 FF 80 ; I2C reset
40 FF 80 ; I2C reset
40 FF 80 ; I2C reset
End


##Scripts 1 CVBS-##
:1-1a CVBS NTSC_PAL-M  480i H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
50 20 00 ; De-assert HDP
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 05 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-1c CVBS NTSC_PAL-M  480i H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 05 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-1d CVBS NTSC_PAL-M  I_P 480p H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 0D ; Frame TBC,3D comb,IP enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-1e CVBS NTSC_PAL-M  480i H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 05 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-1f CVBS NTSC_PAL-M  480p I_P H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
40 DE 90 ; Manual 27Mhz output clock
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 0D ; Frame TBC,I_P, 3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-2a CVBS PAL SECAM PAL_N 576i H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 11 ; Manual chroma VCR Gain
90 12 05 ; Frame TBC, 3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-2c CVBS PAL SECAM PAL_N 576i H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 11 ; Manual chroma VCR Gain
90 12 05 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-2d CVBS PAL SECAM PAL_N I_P 576p H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
40 DE 90 ; Manual 27Mhz output clock
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 11 ; Manual chroma VCR Gain
90 12 0D ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-2e CVBS PAL SECAM PAL_N 576i H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 11 ; Manual chroma VCR Gain
90 12 05 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:1-2f CVBS PAL SECAM PAL_N 576p I_P H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
40 DE 90 ; Manual 27Mhz output clock
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 11 ; Manual chroma VCR Gain
90 12 0D ; Frame TBC,I_P, 3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


##Scripts 2 S-VIDEO NTSC_PAL-M-##
:1-2a S-Video NTSC_PAL-M 480i 10bit H_V HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Of
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 04 ; Frame TBC enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:2-1c S-Video NTSC_PAL-M  480i H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End



:2-1d S-Video NTSC_PAL-M  I_P 480p H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 0C ; Frame TBC, IP enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


:2-1e S-Video NTSC_PAL-M  480i H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:2-1f S-Video NTSC_PAL-M  480p I_P H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 0C ; Frame TBC,I_P enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:2-2a S-Video PAL SECAM PAL_N 576i H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:2-2c S-Video PAL SECAM PAL_N 576i H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:2-2d S-Video PAL SECAM PAL_N I_P 576p H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 0C ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End



:2-2e S-Video PAL SECAM PAL_N 576i H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


:2-2f S-Video PAL SECAM PAL_N 576p I_P H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 09 ; Y/C 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 0A ; ADC0 and ADC2 power Up
4C 02 86 ; Manual Mux enable
4C 03 A0 ; Manual Mux ADC0
4C 04 C0 ; Manual Mux ADC2
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 0C ; Frame TBC,I_P, 3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


##Scripts 3 SDP YPbPr-##
:3-1a YPbPr 480i H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:3-1c YPrPb NTSC_PAL-M 480i H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


:3-1d YPrPb NTSC_PAL-M 480i I_P 480p H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 0C ; Frame TBC,IP enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:3-1e YPrPb NTSC_PAL-M 480i H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End



:3-1f YPrPb NTSC_PAL-M 480i I_P 480p  H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 0C ; Frame TBC,I_P enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:3-2a YPrPb PAL SECAM PAL_N 576i H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:3-2c YPrPb PAL SECAM PAL_N 576i H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End



:3-2d YPrPb PAL SECAM PAL_N 576i I_P 576p H_V_DE 24bit 422 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 82 ; 24 bit 422 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
40 DE 90 ; Manual 27Mhz output clock
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 0C ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End



:3-2e YPrPb PAL SECAM PAL_N 576i H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write 
4C 12 63 ; ADI recommended write 
4C 00 08 ; ADC0, ADC1 and ADC2 powered Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 AA 05 ; Vsync vertical adjustment
94 B0 CC ; Half-Line timing Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 04 ; Frame TBC enable
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


:3-2f YPrPb PAL SECAM PAL_N 576i I_P 576p H_V_DE 36bit 444 out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 11 ; YPrPb 4x1 mode
40 01 00 ; SD core
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 C3 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
4C 00 08 ; ADC0 and ADC2 power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E3 ; Manual luma VCR Gain
90 04 E8 ; Manual luma VCR Gain
90 05 C4 ; Manual chroma VCR Gain
90 06 DC ; Manual chroma VCR Gain
90 12 0C ; Frame TBC,I_P enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

##Scripts 4 CP YPbPr SD-##
:4-1a 480i YPrPb in H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AV02
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 04 ; VID_STD = 0100b for 525i 4X1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 01 ; 10 bit Mode
40 04 82 ; Bus rotation
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 DD D0 ; 2x Clock
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 07 40 ; set AA filter bandwidth to 14MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:4-1b 480i YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 04 ; VID_STD = 0100b for 525i 4X1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 DD D0 ; 2x Clock
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 07 40 ; set AA filter bandwidth to 14MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 YCbCr input
72 16 EC ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:4-1d 480i YPrPb in 444 36bit H_V_DE out HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 04 ; VID_STD = 0100b for 525i 4X1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 07 40 ; set AA filter bandwidth to 14MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 36 bit 444 YCbCr input
72 16 61 ; 444 output
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:4-1e 576i YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 05 ; VID_STD = 0101b for 625i 4X1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 DE D0 ; 2x Clock
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 07 40 ; set AA filter bandwidth to 14MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

##Scripts 4 CP YPbPr ED-##
:4-2a 480p YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 output through AV02
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 0E ; VID_STD = 1110b for 525p 4x1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3) automatic muxing, automatic sync selection
4C 05 07 ; Enable AA filters
4C 07 40 ; set AA filter bandwidth to 14MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:4-2d 576p YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 0F ; VID_STD = 1111b for 625p 4x1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 07 40 ; set AA filter bandwidth to 14MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

##Scripts 4 CP YPbPr HD-##
:4-3a 720p YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 13 ; VID_STD = 010011b for 720p
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 06 A6 ; Invert HS, VS for EIA-861 Compliance
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 06 20 ; Set AA filter bandwidth to 59MHz
4C 07 1F ; Set AA filter bandwidth to 59MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:4-3d 1080i YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 1A ; VID_STD = 11010b for 1125 2x1
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 06 A6 ; Invert HS, VS for EIA-861 Compliance
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 06 20 ; Set AA filter bandwidth to 59MHz
4C 07 1F ; Set AA filter bandwidth to 59MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

:4-3g 1080p YPbPr in_ 422 24bit H_V_DE HDMI:
50 10 05 ; 36 bit enabled
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 1E ; VID_STD= 11110b for 1080p
40 01 01 ; Prim Mode to Component
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 82 ; 24 bit SDR 422
40 05 28 ; Disable AV Codes
40 06 A6 ; Invert HS, VS for EIA-861 Compliance 
40 0C 40 ; Power up Part
40 14 3F ; Max Drive Strength 
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; LLC DLL setting
40 33 43 ; LLC Phase Shift
44 40 5C ; LCVS threshold adjustment 
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 1B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.
44 C3 33 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000 (necessary for rev 1p0 and 1p1)
4C 05 07 ; Enable AA filters
4C 06 20 ; set AA filter bandwidth to 75MHz
4C 07 20 ; set AA filter bandwidth to 75MHz
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 01 ; 24 bit 422 (DDR) YCbCr input
72 16 EC ; 422 output Style3
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End


##Scripts 5 CP Graphics VGA-##

:5-1e 640x480@60 VGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 08 ; VID_STD=01000b for VGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL_PHASE - 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-1f 640x480@72 VGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 09 ; VID_STD=01001b for VGA72
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 42 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 15 ; DLL_PHASE - 010101b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-1g 640x480@75 VGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 0A ; VID_STD=01010b for VGA75
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 42 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 0B ; DLL_PHASE - 001011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-1h 640x480@85 VGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 0B ; VID_STD=01011b for VGA85
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 42 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


##Scripts 5 CP Graphics SVGA-##

:5-2f 800x600@56 SVGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 00 ; VID_STD=00000b for SVGA56
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-2g 800x600@60 SVGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 01 ; VID_STD=00001b for SVGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-2h 800x600@72 SVGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 02 ; VID_STD=00010b for SVGA72
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End



:5-2i 800x600@75 SVGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 03 ; VID_STD=00011b for SVGA75
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-2j 800x600@85 SVGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 04 ; VID_STD=00100b for SVGA85
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


##Scripts 5 CP Graphics XGA-##


:5-3e 1024x768@60 XGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 0C ; VID_STD=01100b for XGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 25 ; DLL_PHASE - 100101b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-3f 1024x768@70 XGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 0D ; VID_STD=01101b for XGA70
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 1A ; DLL_PHASE - 011010b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-3g 1024x768@75 XGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 0E ; VID_STD=01110b for XGA75
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End


:5-3h 1024x768@85 XGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 0F ; VID_STD=01111b for XGA85
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 2A ; DLL_PHASE - 101010b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

##Scripts 5 CP Graphics SXGA-##


:5-4d 1280x1024@60 SXGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 05 ; VID_STD=000101b for SXGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 00 ; DLL_PHASE - 000000b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End



:5-4e 1280x1024@75 SXGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 06 ; VID_STD=000110b for SXGA75
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-4f 1280x1024@85 SXGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C6 ; manual PLL setting
40 17 C0 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C3 ; START HS (part)
44 7E 00 ; START HS
44 7C CF ; END HS (part)
44 7D FF ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 03 ; DE H END (part)
44 8C F6 ; DE H END
44 8B 40 ; DE H START (part)
44 8D 38 ; DE H START
44 8F 41 ; FR_LL
44 90 3A ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 43 ; LCOUNT for STDI CH1
44 AC 00 ; LCOUNT for STDI CH1
44 A5 43 ; NOM START VBI
44 A6 00 ; NOM START VBI (part) NOM END VBI (part)
44 A7 30 ; NOM END VBI
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

##Scripts 5 CP Graphics UXGA-##

:5-5b 1600x1200@60 UXGA RGB in_ 444 24bit H_V_DE HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 16 ; VID_STD=010110b for UXGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 42 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 14 3F ; Max Drive Strength 
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 81 ; LLC DLL Phase
40 33 42 ; LLC DLL Enable
4C 05 0F ; AA Filters Enable
4C 06 20 ; AA Filters BW 146MHz
4C 07 FF ; AA Filters BW 146MHz
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 35 ; Good DLL phase for evaluation board
68 9D 02 ; Recommended EQ setting		
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 24-bit, 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; CSC disabled
72 3B C0 ; Disable VIC transmission from HDMI Tx
72 3C 00 ; Disable VIC transmission from HDMI Tx
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 00 ; Set RGB in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

##Scripts 5 CP Graphics WUXGA-##

:5-6b 1920x1200@60 WUXGA Reduced Blanking RGB in_ 444 24bit H_V_DE HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs 
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 19 ; VID_STD = 011001b for WUXGA60Reduced Blanking
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 42 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 81 ; LLC DLL Phase
40 33 40 ; LLC DLL Enable
4C 05 0F ; AA Filters Enable
4C 06 20 ; AA Filters BW 146MHz
4C 07 FF ; AA Filters BW 146MHz
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 35 ; Good DLL phase for evaluation board
68 9D 02 ; Recommended EQ setting		
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 24-bit, 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; CSC disabled
72 3B C0 ; Disable VIC transmission from HDMI Tx
72 3C 00 ; Disable VIC transmission from HDMI Tx
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 00 ; Set RGB in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

##Scripts 5 CP Graphics WXGA-##
:5-7a 1280x768@60 WXGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 10 ; VID_STD=010000b for WXGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 2A ; DLL_PHASE - 101010b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-7b 1280x768@75 WXGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C6 ; manual PLL setting
40 17 A0 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C0 ; START HS (part)
44 7E 00 ; START HS
44 7C C0 ; END HS (part)
44 7D 00 ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 03 ; DE H END (part)
44 8C E5 ; DE H END
44 8B 40 ; DE H START (part)
44 8D 0E ; DE H START
44 8F 41 ; FR_LL
44 90 DA ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 32 ; LCOUNT for STDI CH1
44 AC 50 ; LCOUNT for STDI CH1
44 A5 64 ; NOM START VBI
44 A6 80 ; NOM START VBI (part) NOM END VBI (part)
44 A7 23 ; NOM END VBI
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 52 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-7c 1280x768@85 WXGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C6 ; manual PLL setting
40 17 B0 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C0 ; START HS (part)
44 7E 00 ; START HS
44 7C C0 ; END HS (part)
44 7D 00 ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 03 ; DE H END (part)
44 8C E6 ; DE H END
44 8B 40 ; DE H START (part)
44 8D 1B ; DE H START
44 8F 41 ; FR_LL
44 90 A1 ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 32 ; LCOUNT for STDI CH1
44 AC 90 ; LCOUNT for STDI CH1
44 A5 65 ; NOM START VBI
44 A6 00 ; NOM START VBI (part) NOM END VBI (part)
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 52 ; HCOUNT ALIGN ADJ
44 A7 27 ; NOM END VBI
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-7d 1280x768@60 reduced blanking WXGAR RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C5 ; manual PLL setting
40 17 A0 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C0 ; START HS (part)
44 7E 00 ; START HS
44 7C C0 ; END HS (part)
44 7D 00 ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 0F ; DE H END (part)
44 8C FD ; DE H END
44 8B 4F ; DE H START (part)
44 8D 5E ; DE H START
44 8F 42 ; FR_LL (part)
44 90 5C ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 31 ; LCOUNT for STDI CH1
44 AC 60 ; LCOUNT for STDI CH1 (part)
44 A5 62 ; NOM START VBI
44 A6 A0 ; NOM START VBI (part) NOM END VBI (part)
44 A7 14 ; NOM END VBI 
44 BE 0A ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

##Scripts 5 CP Graphics MISC-##
:5-8a 1280x720@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C6 ; manual PLL setting
40 17 72 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C0 ; START HS (part)
44 7E 00 ; START HS
44 7C C0 ; END HS (part)
44 7D 00 ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 0F ; DE H END (part)
44 8C C6 ; DE H END
44 8B 4F ; DE H START (part)
44 8D CB ; DE H START
44 8F 42 ; FR_LL (part)
44 90 7C ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 2E ; LCOUNT for STDI CH1
44 AC E0 ; LCOUNT for STDI CH1 (part)
44 A5 2E ; NOM START VBI
44 A6 A0 ; NOM START VBI (part) NOM END VBI (part)
44 A7 1A ; NOM END VBI 
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-8b 1920x1080@60 with reduced blanking RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C8 ; manual PLL setting
40 17 20 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C0 ; START HS (part)
44 7E 00 ; START HS
44 7C C3 ; END HS (part)
44 7D FF ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 00 ; DE H END (part)
44 8C 11 ; DE H END
44 8B 4B ; DE H START (part)
44 8D E6 ; DE H START
44 8F 41 ; FR_LL (part)
44 90 AE ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 45 ; LCOUNT for STDI CH1
44 AC 70 ; LCOUNT for STDI CH1 (part)
44 A5 45 ; NOM START VBI
44 A6 50 ; NOM START VBI (part) NOM END VBI (part)
44 A7 1D ; NOM END VBI 
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-8c 1920x1080@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 07 ; autographics
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 16 C8 ; manual PLL setting
40 17 98 ; manual PLL setting
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 7C C0 ; START HS (part)
44 7E 00 ; START HS
44 7C C3 ; END HS (part)
44 7D FF ; END HS
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 8B 4F ; DE H END (part)
44 8C ED ; DE H END
44 8B 4F ; DE H START (part)
44 8D 20 ; DE H START
44 8F 41 ; FR_LL (part)
44 90 A8 ; FR_LL
44 91 00 ; Set to progressive mode
44 AB 46 ; LCOUNT for STDI CH1
44 AC 50 ; LCOUNT for STDI CH1 (part)
44 A5 46 ; NOM START VBI
44 A6 20 ; NOM START VBI (part) NOM END VBI (part)
44 A7 2A ; NOM END VBI 
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

:5-8d 1360x768@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C7 ; set PLL for 1792 samples per line
40 17 00 ; set PLL for 1792 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C F8 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 1C ; set horizontal DE start/end position
44 8F 02 ; configure freerun parameters FR_LL
44 90 58 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 31 ; set vertical DE start/end position (odd/prog)
44 A6 90 ; set vertical DE start/end position (odd/prog)
44 A7 19 ; set vertical DE start/end position (odd/prog)
44 A8 18 ; set vertical DE start/end position (even)
44 A9 B1 ; set vertical DE start/end position (even)
44 AA 99 ; set vertical DE start/end position (even)
44 AB 31 ; configure freerun parameter LCOUNT_MAX
44 AC B0 ; configure freerun parameter LCOUNT_MAX
End

:5-8f 720x400@70 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C3 ; set PLL for 900 samples per line
40 17 84 ; set PLL for 900 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 4C ; set horizontal DE start/end position
44 8C 0B ; set horizontal DE start/end position
44 8B 4C ; set horizontal DE start/end position
44 8D F6 ; set horizontal DE start/end position
44 8F 03 ; configure freerun parameters FR_LL
44 90 8E ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 1B ; set vertical DE start/end position (odd/prog)
44 A6 50 ; set vertical DE start/end position (odd/prog)
44 A7 25 ; set vertical DE start/end position (odd/prog)
44 A8 0D ; set vertical DE start/end position (even)
44 A9 40 ; set vertical DE start/end position (even)
44 AA ED ; set vertical DE start/end position (even)
44 AB 1C ; configure freerun parameter LCOUNT_MAX
44 AC 10 ; configure freerun parameter LCOUNT_MAX
End

:5-8h 720x350@70 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C3 ; set PLL for 900 samples per line
40 17 84 ; set PLL for 900 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 4C ; set horizontal DE start/end position
44 8C 0B ; set horizontal DE start/end position
44 8B 4C ; set horizontal DE start/end position
44 8D F6 ; set horizontal DE start/end position
44 8F 03 ; configure freerun parameters FR_LL
44 90 8E ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 19 ; set vertical DE start/end position (odd/prog)
44 A6 D0 ; set vertical DE start/end position (odd/prog)
44 A7 3F ; set vertical DE start/end position (odd/prog)
44 A8 0B ; set vertical DE start/end position (even)
44 A9 C0 ; set vertical DE start/end position (even)
44 AA EE ; set vertical DE start/end position (even)
44 AB 1C ; configure freerun parameter LCOUNT_MAX
44 AC 10 ; configure freerun parameter LCOUNT_MAX
End

:5-8j 640x400@85 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C3 ; set PLL for 832 samples per line
40 17 40 ; set PLL for 832 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C FA ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 00 ; set horizontal DE start/end position
44 8F 02 ; configure freerun parameters FR_LL
44 90 F4 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 1B ; set vertical DE start/end position (odd/prog)
44 A6 D0 ; set vertical DE start/end position (odd/prog)
44 A7 2D ; set vertical DE start/end position (odd/prog)
44 A8 0D ; set vertical DE start/end position (even)
44 A9 E0 ; set vertical DE start/end position (even)
44 AA F5 ; set vertical DE start/end position (even)
44 AB 1B ; configure freerun parameter LCOUNT_MAX
44 AC D0 ; configure freerun parameter LCOUNT_MAX
End

:5-8l 640x350@85 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C3 ; set PLL for 832 samples per line
40 17 40 ; set PLL for 832 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C FA ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 00 ; set horizontal DE start/end position
44 8F 02 ; configure freerun parameters FR_LL
44 90 F4 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 19 ; set vertical DE start/end position (odd/prog)
44 A6 E0 ; set vertical DE start/end position (odd/prog)
44 A7 40 ; set vertical DE start/end position (odd/prog)
44 A8 0B ; set vertical DE start/end position (even)
44 A9 F0 ; set vertical DE start/end position (even)
44 AA EF ; set vertical DE start/end position (even)
44 AB 1B ; configure freerun parameter LCOUNT_MAX
44 AC D0 ; configure freerun parameter LCOUNT_MAX
End

:5-8n 720x400@85 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C3 ; set PLL for 936 samples per line
40 17 A8 ; set PLL for 936 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C FA ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 01 ; set horizontal DE start/end position
44 8F 02 ; configure freerun parameters FR_LL
44 90 F3 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 1B ; set vertical DE start/end position (odd/prog)
44 A6 E0 ; set vertical DE start/end position (odd/prog)
44 A7 2E ; set vertical DE start/end position (odd/prog)
44 A8 0D ; set vertical DE start/end position (even)
44 A9 F0 ; set vertical DE start/end position (even)
44 AA F6 ; set vertical DE start/end position (even)
44 AB 1B ; configure freerun parameter LCOUNT_MAX
44 AC E0 ; configure freerun parameter LCOUNT_MAX
End

:5-8p 848x480@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C4 ; set PLL for 1088 samples per line
40 17 40 ; set PLL for 1088 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 40 ; set horizontal DE start/end position
44 8C 12 ; set horizontal DE start/end position
44 8B 40 ; set horizontal DE start/end position
44 8D 10 ; set horizontal DE start/end position
44 8F 03 ; configure freerun parameters FR_LL
44 90 9B ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 20 ; set vertical DE start/end position (odd/prog)
44 A6 00 ; set vertical DE start/end position (odd/prog)
44 A7 20 ; set vertical DE start/end position (odd/prog)
44 A8 0F ; set vertical DE start/end position (even)
44 A9 D1 ; set vertical DE start/end position (even)
44 AA 10 ; set vertical DE start/end position (even)
44 AB 20 ; configure freerun parameter LCOUNT_MAX
44 AC 50 ; configure freerun parameter LCOUNT_MAX
End

:5-8r 1152x864@75 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 12 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C6 ; set PLL for 1600 samples per line
40 17 40 ; set PLL for 1600 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C F2 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 50 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 A8 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 38 ; set vertical DE start/end position (odd/prog)
44 A6 40 ; set vertical DE start/end position (odd/prog)
44 A7 24 ; set vertical DE start/end position (odd/prog)
44 A8 1C ; set vertical DE start/end position (even)
44 A9 21 ; set vertical DE start/end position (even)
44 AA D4 ; set vertical DE start/end position (even)
44 AB 38 ; configure freerun parameter LCOUNT_MAX
44 AC 40 ; configure freerun parameter LCOUNT_MAX
End

:5-8t 1280x960@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 12 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C7 ; set PLL for 1800 samples per line
40 17 08 ; set PLL for 1800 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C D9 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 53 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 DD ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 3E ; set vertical DE start/end position (odd/prog)
44 A6 80 ; set vertical DE start/end position (odd/prog)
44 A7 28 ; set vertical DE start/end position (odd/prog)
44 A8 1F ; set vertical DE start/end position (even)
44 A9 42 ; set vertical DE start/end position (even)
44 AA 08 ; set vertical DE start/end position (even)
44 AB 3E ; configure freerun parameter LCOUNT_MAX
44 AC 80 ; configure freerun parameter LCOUNT_MAX
End

:5-8v 1280x960@85 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 12 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C6 ; set PLL for 1728 samples per line
40 17 C0 ; set PLL for 1728 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C F6 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 38 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 4D ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 3F ; set vertical DE start/end position (odd/prog)
44 A6 30 ; set vertical DE start/end position (odd/prog)
44 A7 33 ; set vertical DE start/end position (odd/prog)
44 A8 1F ; set vertical DE start/end position (even)
44 A9 92 ; set vertical DE start/end position (even)
44 AA 13 ; set vertical DE start/end position (even)
44 AB 3F ; configure freerun parameter LCOUNT_MAX
44 AC 30 ; configure freerun parameter LCOUNT_MAX
End

:5-8x 1400x1050@60 reduced blanking RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C6 ; set PLL for 1560 samples per line
40 17 18 ; set PLL for 1560 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 4C ; set horizontal DE start/end position
44 8C 01 ; set horizontal DE start/end position
44 8B 4C ; set horizontal DE start/end position
44 8D 48 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 BA ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 43 ; set vertical DE start/end position (odd/prog)
44 A6 60 ; set vertical DE start/end position (odd/prog)
44 A7 1C ; set vertical DE start/end position (odd/prog)
44 A8 21 ; set vertical DE start/end position (even)
44 A9 A2 ; set vertical DE start/end position (even)
44 AA 29 ; set vertical DE start/end position (even)
44 AB 43 ; configure freerun parameter LCOUNT_MAX
44 AC 80 ; configure freerun parameter LCOUNT_MAX
End

:5-8z 1400x1050@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C7 ; set PLL for 1864 samples per line
40 17 48 ; set PLL for 1864 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C E3 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 17 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 B6 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 43 ; set vertical DE start/end position (odd/prog)
44 A6 F0 ; set vertical DE start/end position (odd/prog)
44 A7 25 ; set vertical DE start/end position (odd/prog)
44 A8 21 ; set vertical DE start/end position (even)
44 A9 E2 ; set vertical DE start/end position (even)
44 AA 32 ; set vertical DE start/end position (even)
44 AB 44 ; configure freerun parameter LCOUNT_MAX
44 AC 10 ; configure freerun parameter LCOUNT_MAX
End

:5-8ab 1440x1050@75 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C7 ; set PLL for 1896 samples per line
40 17 68 ; set PLL for 1896 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C D4 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 21 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 5C ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 44 ; set vertical DE start/end position (odd/prog)
44 A6 90 ; set vertical DE start/end position (odd/prog)
44 A7 2F ; set vertical DE start/end position (odd/prog)
44 A8 22 ; set vertical DE start/end position (even)
44 A9 32 ; set vertical DE start/end position (even)
44 AA 3C ; set vertical DE start/end position (even)
44 AB 44 ; configure freerun parameter LCOUNT_MAX
44 AC B0 ; configure freerun parameter LCOUNT_MAX
End

:5-8ad 1280x768@70 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C6 ; set PLL for 1696 samples per line
40 17 A0 ; set PLL for 1696 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C E5 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 0E ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 FE ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 32 ; set vertical DE start/end position (odd/prog)
44 A6 00 ; set vertical DE start/end position (odd/prog)
44 A7 20 ; set vertical DE start/end position (odd/prog)
44 A8 19 ; set vertical DE start/end position (even)
44 A9 01 ; set vertical DE start/end position (even)
44 AA A0 ; set vertical DE start/end position (even)
44 AB 32 ; configure freerun parameter LCOUNT_MAX
44 AC 00 ; configure freerun parameter LCOUNT_MAX
End

:5-8af 1280x768@72 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C6 ; set PLL for 1696 samples per line
40 17 A0 ; set PLL for 1696 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C E5 ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 0E ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 F2 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 32 ; set vertical DE start/end position (odd/prog)
44 A6 10 ; set vertical DE start/end position (odd/prog)
44 A7 21 ; set vertical DE start/end position (odd/prog)
44 A8 19 ; set vertical DE start/end position (even)
44 A9 01 ; set vertical DE start/end position (even)
44 AA A1 ; set vertical DE start/end position (even)
44 AB 32 ; configure freerun parameter LCOUNT_MAX
44 AC 10 ; configure freerun parameter LCOUNT_MAX
End

:5-8ag 640x480@70 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C3 ; set PLL for 816 samples per line
40 17 30 ; set PLL for 816 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 4C ; set horizontal DE start/end position
44 8C 00 ; set horizontal DE start/end position
44 8B 4C ; set horizontal DE start/end position
44 8D F9 ; set horizontal DE start/end position
44 8F 03 ; configure freerun parameters FR_LL
44 90 34 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 1F ; set vertical DE start/end position (odd/prog)
44 A6 40 ; set vertical DE start/end position (odd/prog)
44 A7 14 ; set vertical DE start/end position (odd/prog)
44 A8 0F ; set vertical DE start/end position (even)
44 A9 A1 ; set vertical DE start/end position (even)
44 AA 04 ; set vertical DE start/end position (even)
44 AB 1F ; configure freerun parameter LCOUNT_MAX
44 AC 40 ; configure freerun parameter LCOUNT_MAX
End

:5-8ai 800x600@70 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C4 ; set PLL for 1040 samples per line
40 17 10 ; set PLL for 1040 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 4F ; set horizontal DE start/end position
44 8C F5 ; set horizontal DE start/end position
44 8B 4F ; set horizontal DE start/end position
44 8D FD ; set horizontal DE start/end position
44 8F 02 ; configure freerun parameters FR_LL
44 90 8D ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 27 ; set vertical DE start/end position (odd/prog)
44 A6 10 ; set vertical DE start/end position (odd/prog)
44 A7 19 ; set vertical DE start/end position (odd/prog)
44 A8 13 ; set vertical DE start/end position (even)
44 A9 81 ; set vertical DE start/end position (even)
44 AA 45 ; set vertical DE start/end position (even)
44 AB 27 ; configure freerun parameter LCOUNT_MAX
44 AC 10 ; configure freerun parameter LCOUNT_MAX
End

:5-8ak 1440x900@60 reduced blanking RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C6 ; set PLL for 1600 samples per line
40 17 40 ; set PLL for 1600 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 4C ; set horizontal DE start/end position
44 8C 02 ; set horizontal DE start/end position
44 8B 4C ; set horizontal DE start/end position
44 8D 40 ; set horizontal DE start/end position
44 8F 02 ; configure freerun parameters FR_LL
44 90 04 ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 39 ; set vertical DE start/end position (odd/prog)
44 A6 C0 ; set vertical DE start/end position (odd/prog)
44 A7 18 ; set vertical DE start/end position (odd/prog)
44 A8 1C ; set vertical DE start/end position (even)
44 A9 D1 ; set vertical DE start/end position (even)
44 AA DA ; set vertical DE start/end position (even)
44 AB 39 ; configure freerun parameter LCOUNT_MAX
44 AC E0 ; configure freerun parameter LCOUNT_MAX
End

:5-8am 1440x900@60 RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
40 19 80 ; enable LLC DLL
40 33 40 ; select DLL for LLC clock
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 BE 02 ; HCOUNT ALIGN ADJ
44 BF 32 ; HCOUNT ALIGN ADJ
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI Recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL Phase, 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
40 00 07 ; Set VID_STD to 0b000111 for autographics
40 01 02 ; Set PRIM_MODE to 0b0010 for graphics mode
40 16 C7 ; set PLL for 1904 samples per line
40 17 70 ; set PLL for 1904 samples per line
44 81 D0 ; enable blue screen freerun in autographics mode
44 8B 43 ; set horizontal DE start/end position
44 8C EC ; set horizontal DE start/end position
44 8B 43 ; set horizontal DE start/end position
44 8D 17 ; set horizontal DE start/end position
44 8F 01 ; configure freerun parameters FR_LL
44 90 FF ; configure freerun parameters FR_LL
44 91 00 ; set CP core to progressive mode
44 A5 3A ; set vertical DE start/end position (odd/prog)
44 A6 40 ; set vertical DE start/end position (odd/prog)
44 A7 20 ; set vertical DE start/end position (odd/prog)
44 A8 1D ; set vertical DE start/end position (even)
44 A9 11 ; set vertical DE start/end position (even)
44 AA E2 ; set vertical DE start/end position (even)
44 AB 3A ; configure freerun parameter LCOUNT_MAX
44 AC 60 ; configure freerun parameter LCOUNT_MAX
End

##Scripts 6 HDMI-##

:6-1d Port A, 480i,576i,240p,288p,480p 576p YPrPb 444 in, RGB 444 out, Through HDMI (Fast Switching)VIC[1-3,6-14,17,18,21-29,30]:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 24-bit, 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End 


:6-1e Port A, 720p,1080i YPrPb 444 in, RGB 444 out, Through HDMI (Fast Switching)VIC[4,5,19,20]:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert VS,HS pins
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 24-bit, 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End 



:6-1f Port A, 1080p YPrPb 444 in, RGB 444 out, Through HDMI (Fast Switching)VIC[16,31,32]:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert VS,HS pins
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 3F ; Max Drive Strength 
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 43 ; LLC Phase Shift
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 24-bit, 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End 


##Scripts 6 HDMI PCM Audio##
:6-4a - 1920 x 1080p60, YPrPb 444 in, YPrPb 444 out, 32kHz 8ch, VIC 16:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert HS,VS for compliance
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 3F ; Max Drive Strength 
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set 'N' value at 4096
72 02 10 ; Set 'N' value at 4096
72 03 00 ; Set 'N' value at 4096
72 14 70 ; 8 ch
72 15 30 ; 24-bit, 444 YPrPb input, 32kHz fs
72 16 60 ; YPrPb 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 55 40 ; Set YCrCb 444 in AVI infoframe
72 56 08 ; Set active format aspect
72 73 07 ; Info frame Ch count to 8
72 76 1F ; Set speaker allocation for 8 channels
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Select HDMI mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
50 20 00 ; HPD
End

:6-4b - 1920 x 1080p60, YPrPb 444 in, YPrPb 444 out, 48kHz 8 Ch VIC 16:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert HS,VS for compliance
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 3F ; Max Drive Strength 
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 14 70 ; Set Ch count in the channel status to 8.
72 15 20 ; 24-bit, 444 YPrPb input, 48kHz fs
72 16 60 ; YPrPb 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 55 40 ; Set YCrCb 444 in AVI infoframe
72 56 08 ; Set active format aspect
72 73 07 ; Info frame Ch count to 8
72 76 1F ; Set speaker allocation for 8 channels
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Select HDMI mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End



:6-4c - 1920 x 1080p60, YPrPb 444 in, YPrPb 444 out, 192kHz 8Ch, VIC 16:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert HS,VS for compliance
40 0C 40 ; Power up part and power down VDP
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 14 3F ; Max Drive Strength 
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set 'N' value at 24576
72 02 60 ; Set 'N' value at 24576
72 03 00 ; Set 'N' value at 24576
72 14 70 ; Set to 8 Ch
72 15 E0 ; 24-bit, 444 YPrPb input, 192kHz fs
72 16 60 ; YPrPb 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 55 40 ; Set YCrCb 444 in AVI infoframe
72 56 08 ; Set active format aspect
72 73 07 ; Info frame Ch count to 8
72 76 1F ; Set speaker allocation for 8 channels
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Select HDMI mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
50 20 00 ; HPD
End



##Scripts 6 HDMI- HBR Audio##
:6-2a Port A, 1080p60 YPrPb 444 in, RGB 444 out, Through HDMI (Fast Switching):
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert HS and VS for 861 compliance.
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 7F ; Disable Tristate of Pins
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL adjustment
40 33 40 ; LLC DLL Enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 00 ; Setting MCLK to 128Fs
68 44 85 ; ADI reccommended writes
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set N for 192KHz sampling and 148MHz pixel clock
72 02 60 ; Set N for 192KHz sampling and 148MHz pixel clock
72 03 00 ; Set N for 192KHz sampling and 148MHz pixel clock
72 15 00 ; 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVI infoframe
72 56 08 ; Set active format aspect
72 73 07 ; Info frame Ch count to 8
72 76 1F ; Set speaker allocation for 8 channels
72 96 20 ; HPD interrupt clear
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Select HDMI mode
72 DE 9C ; ADI Recommended Write
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
72 0A 30 ; Setup for 128Fs 
72 0B EE ; Enable SPDIF and MCLK in.
72 47 00 ; Synchronising PaPb HBR syncword
72 47 40 ; Synchronising PaPb HBR syncword
72 47 00 ; Synchronising PaPb HBR syncword
End


:6-2b Port A, 480P60, 480i  4X1 YPrPb 444 in, RGB 444 out, Through HDMI (Pix Rep x4(Fast Switching):
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A0 ; HS and VS for 861 compliance.
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 7F ; Disable Tristate of Pins
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL adjustment
40 33 40 ; LLC DLL Enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 00 ; Setting MCLK to 128Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set N for 192KHz sampling and 148MHz pixel clock
72 02 60 ; Set N for 192KHz sampling and 148MHz pixel clock
72 03 00 ; Set N for 192KHz sampling and 148MHz pixel clock
72 15 00 ; 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; Disable CSC
72 3B FE ; Pix Rep x4 
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVI infoframe
72 56 08 ; Set active format aspect
72 73 07 ; Info frame Ch count to 8
72 76 1F ; Set speaker allocation for 8 channels
72 96 20 ; HPD interrupt clear
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Select HDMI mode
72 DE 9C ; ADI Recommended Write
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
72 0A 30 ; Setup for 128Fs 
72 0B EE ; Enable SPDIF and MCLK in.
72 47 00 ; Synchronising PaPb HBR syncword
72 47 40 ; Synchronising PaPb HBR syncword
72 47 00 ; Synchronising PaPb HBR syncword
End



##Scripts 6 HDMI-DSD Audio##
:6-3a Port A YPrPb 444 in, RGB 444 out, DSD Audio:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; HS and VS for 861 compliance.
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 3F ; Max Drive Strength 
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set 'N' value
72 02 18 ; Set 'N' value
72 03 80 ; Set 'N' value
72 0A 21 ; Enable DSD with MCLK = 256Fs
72 15 00 ; 24-bit, 444 YPrPb input, 44.1kHz fs
72 16 60 ; YPrPb 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 46 FF ; Enable dsd pins
72 49 A8 ; Set dither mode - 12-to-10 bit
72 4C 06 ; Set 12 bit output
72 96 20 ; HPD interrupt clear
72 55 40 ; Set YCrCb 444 in AVI infoframe
72 56 08 ; Set active format aspect
72 73 05 ; Info frame Ch count to 6
72 74 08 ; Set info frame for Fs = 44.1KHz.
72 76 0B ; Set speaker allocation for 6 channels
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Select HDMI mode
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End 


##Scripts 7 Simultaneous Mode ##
:7-1a Port A, CVBS out through HDMI With HDMI Audio(PCM):
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 00 ; CVBS 2x1 simultaneous mode
40 01 84 ; Sim mode with HDMI audio
40 02 F4 ; Auto input color space, Limited Range YPbPr Output
40 03 42 ; 36 bit 444 mode
40 04 62 ; Output bus rotation (default)
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
4C 0C 1F ; ADI recommended write 
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 12 00 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
50 20 00 ; De-assert HDP
44 BA 01 ; Set HDMI FreeRun
44 3E 00 ; Disable CP Pregain Block
44 6C 00 ; Use fixed clamp values
4C B5 01 ; Setting MCLK to 256Fs
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 18 ; Enable clock terminators
68 0D 34 ; ADI recommended write		
68 1A 8A ; Unmute audio
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write ES3/Final silicon
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 18 ; Disable ISRC clearing bit, Improve robustness
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 67 20 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; HDMI Recommended write
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 00 ; 24-bit, 444 YPrPb input
72 16 60 ; YPrPb 444
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 40 ; Set YCrCb 444 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
50 3E 70 ; LRCLK from HDMI Rx to Codec
50 3F 70 ; Serial clock (BCLK) from HDMI Rx to Codec
50 50 01 ; 12S to Codec is 12S0 from HDMI Rx
50 51 01 ; SPDIF from HDMI Rx to Codec 
50 52 02 ; MCLK from HDMI Rx to Codec
26 C8 03 ; Unmute DAC
26 EC 25 ; DAC clk = ADC clk = ICLK2 = MLCKI (12.288MHz)
26 EE 08 ; ICLK1 = MCLKI (12.288MHz)
26 F0 C0 ; PLL1 MLKC = PLL2 MCLK = MCLKI (12.288MHz)
26 0C 01 ; Record Port slave, 24 bits, I2S
26 0E 31 ; Auxiliary Record Port master (ICLK2), 24 bits, I2S - to check, connect auxiliary record port clocksto record port
End 

##Scripts 8 EDID ##
:8-1 EDID Download VGA :
40 FF 80 ; I2C reset
40 F9 64 ; KSV 
40 FA 6C ; EDID
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
64 77 50 ; Enable VGA Segment   
6C 00 00 ;
6C 01 FF ;
6C 02 FF ;
6C 03 FF ;
6C 04 FF ;
6C 05 FF ;
6C 06 FF ;
6C 07 00 ;
6C 08 06 ;
6C 09 96 ;
6C 0A 48 ;
6C 0B 44 ;
6C 0C 01 ;
6C 0D 00 ;
6C 0E 00 ;
6C 0F 00 ;
6C 10 30 ;
6C 11 13 ;
6C 12 01 ;
6C 13 03 ;
6C 14 0E ;
6C 15 31 ;
6C 16 1C ;
6C 17 A0 ;
6C 18 2A ;
6C 19 AA ;
6C 1A 33 ;
6C 1B A4 ;
6C 1C 55 ;
6C 1D 48 ;
6C 1E 93 ;
6C 1F 25 ;
6C 20 10 ;
6C 21 45 ;
6C 22 47 ;
6C 23 FF ;
6C 24 FF ;
6C 25 80 ;
6C 26 81 ;
6C 27 8F ;
6C 28 81 ;
6C 29 99 ;
6C 2A A9 ;
6C 2B 40 ;
6C 2C 61 ;
6C 2D 59 ;
6C 2E 45 ;
6C 2F 59 ;
6C 30 31 ;
6C 31 59 ;
6C 32 71 ;
6C 33 4A ;
6C 34 81 ;
6C 35 40 ;
6C 36 02 ;
6C 37 3A ;
6C 38 80 ;
6C 39 18 ;
6C 3A 71 ;
6C 3B 38 ;
6C 3C 2D ;
6C 3D 40 ;
6C 3E 46 ;
6C 3F 28 ;
6C 40 55 ;
6C 41 00 ;
6C 42 E8 ;
6C 43 12 ;
6C 44 11 ;
6C 45 00 ;
6C 46 00 ;
6C 47 18 ;
6C 48 01 ;
6C 49 1D ;
6C 4A 00 ;
6C 4B 72 ;
6C 4C 51 ;
6C 4D D0 ;
6C 4E 1E ;
6C 4F 20 ;
6C 50 46 ;
6C 51 28 ;
6C 52 55 ;
6C 53 00 ;
6C 54 E8 ;
6C 55 12 ;
6C 56 11 ;
6C 57 00 ;
6C 58 00 ;
6C 59 18 ;
6C 5A 00 ;
6C 5B 00 ;
6C 5C 00 ;
6C 5D FC ;
6C 5E 00 ;
6C 5F 48 ;
6C 60 44 ;
6C 61 4D ;
6C 62 49 ;
6C 63 20 ;
6C 64 54 ;
6C 65 56 ;
6C 66 0A ;
6C 67 20 ;
6C 68 20 ;
6C 69 20 ; 
6C 6A 20 ;
6C 6B 20 ;
6C 6C 00 ;
6C 6D 00 ;
6C 6E 00 ;
6C 6F FD ;
6C 70 00 ;
6C 71 1D ;
6C 72 56 ;
6C 73 0F ;
6C 74 6F ;
6C 75 11 ;
6C 76 00 ;
6C 77 0A ;
6C 78 20 ;
6C 79 20 ;
6C 7A 20 ;
6C 7B 20 ;
6C 7C 20 ;
6C 7D 20 ;
6C 7E 00 ; 128 bytes only
6C 7F 10 ;  
64 7F 84 ; Enable VGA EDID  
End


:8-2 EDID Download HDMI :
40 FF 80 ; I2C reset
40 F9 64 ; KSV 
40 FA 6C ; EDID
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
64 77 50 ; Enable VGA Segment   
64 77 00 ; Disable the Internal EDID for all 4 Ports - Programming HDMI EDID 
6C 00 00 ;
6C 01 FF ;
6C 02 FF ; 
6C 03 FF ;
6C 04 FF ;
6C 05 FF ;
6C 06 FF ;
6C 07 00 ;
6C 08 06 ;
6C 09 96 ;
6C 0A 48 ;
6C 0B 44 ;
6C 0C 01 ; 
6C 0D 00 ;
6C 0E 00 ;
6C 0F 00 ;
6C 10 25 ;
6C 11 10 ;
6C 12 01 ;
6C 13 03 ;
6C 14 80 ;
6C 15 31 ;
6C 16 1C ;
6C 17 A0 ;
6C 18 2A ;
6C 19 AA ;
6C 1A 33 ;
6C 1B A4 ;
6C 1C 55 ;
6C 1D 48 ;
6C 1E 93 ;
6C 1F 25 ;
6C 20 10 ;
6C 21 45 ;
6C 22 47 ;
6C 23 FF ;
6C 24 FF ;
6C 25 80 ;
6C 26 81 ;
6C 27 8F ;
6C 28 81 ;
6C 29 99 ;
6C 2A A9 ;
6C 2B 40 ;
6C 2C 61 ;
6C 2D 59 ;
6C 2E 45 ;
6C 2F 59 ;
6C 30 31 ;
6C 31 59 ;
6C 32 71 ;
6C 33 4A ;
6C 34 81 ;
6C 35 40 ;
6C 36 02 ;
6C 37 3A ;
6C 38 80 ;
6C 39 18 ;
6C 3A 71 ;
6C 3B 38 ;
6C 3C 2D ;
6C 3D 40 ;
6C 3E 46 ;
6C 3F 28 ;
6C 80 02 ;
6C 81 03 ;
6C 82 21 ;
6C 83 71 ;
6C 84 4D ;
6C 85 90 ;
6C 86 04 ;
6C 87 03 ;
6C 88 12 ;
6C 89 01 ;
6C 8A 13 ;
6C 8B 11 ;
6C 8C 07 ;
6C 8D 05 ;
6C 8E 06 ;
6C 8F 22 ;
6C 90 14 ;
6C 91 15 ;
6C 92 23 ;
6C 93 09 ;
6C 94 07 ;
6C 95 07 ;
6C 96 83 ;
6C 97 4F ;
6C 98 00 ;
6C 99 00 ;
6C 9A 66 ;
6C 9B 03 ;
6C 9C 0C ;
6C 9D 00 ;
6C 9E 10 ;
6C 9F 00 ;
6C A0 80 ;
6C A1 01 ;
6C A2 1D ;
6C A3 00 ;
6C A4 72 ;
6C A5 51 ;
6C A6 D0 ;
6C A7 1E ;
6C A8 20 ;
6C A9 6E ;
6C AA 28 ;
6C AB 55 ;
6C AC 00 ;
6C AD E8 ;
6C AE 12 ;
6C AF 11 ;
6C B0 00 ;
6C B1 00 ;
6C B2 1E ;
6C B3 8C ;
6C B4 0A ;
6C B5 D0 ;
6C B6 90 ;
6C B7 20 ;
6C B8 40 ;
6C B9 31 ;
6C BA 20 ;
6C BB 0C ;
6C BC 40 ;
6C BD 55 ;
6C BE 00 ;
6C BF E8 ;
6C 40 55 ;
6C 41 00 ;
6C 42 E8 ;
6C 43 12 ;
6C 44 11 ;
6C 45 00 ;
6C 46 00 ;
6C 47 18 ;
6C 48 01 ;
6C 49 1D ;
6C 4A 00 ;
6C 4B 72 ;
6C 4C 51 ;
6C 4D D0 ;
6C 4E 1E ;
6C 4F 20 ;
6C 50 46 ;
6C 51 28 ;
6C 52 55 ;
6C 53 00 ;
6C 54 E8 ;
6C 55 12 ;
6C 56 11 ;
6C 57 00 ;
6C 58 00 ;
6C 59 18 ;
6C 5A 00 ;
6C 5B 00 ;
6C 5C 00 ;
6C 5D FC ;
6C 5E 00 ;
6C 5F 48 ;
6C 60 44 ;
6C 61 4D ;
6C 62 49 ;
6C 63 20 ;
6C 64 54 ;
6C 65 56 ;
6C 66 0A ;
6C 67 20 ;
6C 68 20 ;
6C 69 20 ;
6C 6A 20 ;
6C 6B 20 ;
6C 6C 00 ;
6C 6D 00 ;
6C 6E 00 ;
6C 6F FD ;
6C 70 00 ; 
6C 71 1D ;
6C 72 56 ;
6C 73 0F ;
6C 74 6F ;
6C 75 11 ;
6C 76 00 ;
6C 77 0A ;
6C 78 20 ;
6C 79 20 ;
6C 7A 20 ;
6C 7B 20 ;
6C 7C 20 ;
6C 7D 20 ;
6C 7E 01 ;
6C 7F AB ;
6C C0 12 ;
6C C1 11 ;
6C C2 00 ;
6C C3 00 ;
6C C4 18 ;
6C C5 8C ;
6C C6 0A ;
6C C7 D0 ;
6C C8 8A ;
6C C9 20 ;
6C CA E0 ;
6C CB 2D ;
6C CC 10 ;
6C CD 10 ;
6C CE 3E ;
6C CF 96 ;
6C D0 00 ;
6C D1 E8 ;
6C D2 12 ;
6C D3 11 ;
6C D4 00 ;
6C D5 00 ;
6C D6 18 ;
6C D7 01 ;
6C D8 1D ;
6C D9 80 ;
6C DA 18 ;
6C DB 71 ;
6C DC 1C ;
6C DD 16 ;
6C DE 20 ;
6C DF 58 ;
6C E0 28 ;
6C E1 25 ;
6C E2 00 ;
6C E3 E8 ;
6C E4 12 ;
6C E5 11 ;
6C E6 00 ;
6C E7 00 ;
6C E8 98 ;
6C E9 01 ;
6C EA 1D ;
6C EB 00 ;
6C EC BC ;
6C ED 52 ;
6C EE D0 ;
6C EF 1E ;
6C F0 20 ;
6C F1 B8 ;
6C F2 28 ;
6C F3 55 ;
6C F4 40 ;
6C F5 E8 ;
6C F6 12 ;
6C F7 11 ;
6C F8 00 ;
6C F9 00 ;
6C FA 1E ; 
6C FB 00 ;
6C FC 00 ;
6C FD 00 ;
6C FE 00 ;
6C FF A5 ;
64 77 00 ; Set the Most Significant Bit of the SPA location to 0
64 70 20 ; Set the SPA for port B
64 71 00 ; Set the SPA for port B. The checksum should be set to 0x95
64 72 30 ; Set the SPA for port C
64 73 00 ; Set the SPA for port C. The checksum should be set to 0x85
64 74 40 ; Set the SPA for port D
64 75 00 ; Set the SPA for port D. The checksum should be set to 0x75
64 76 9E ; Set the Least Significant Byte of the SPA location
64 77 0F ; Enable the Internal EDID for all 4 Ports
End


##Script 9 DVI##
:DVI RGB In, RGB Out DVI:        
;50 10 05 ; 36 output through AV02
;50 11 08 ; Bus Reversal
;50 19 10 ; ADV7844 Mode
;50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 01 06 ; Prim_Mode =110b HDMI-GR
40 02 F2 ; Auto CSC, RGB out
40 03 42 ; 36 bit SDR 444 Mode 0
40 05 28 ; AV Codes Off
40 06 A6 ; Invert HS and VS for 861 compliance.
68 C1 FF ; HDMI power control (power saving)
68 C2 FF ; HDMI power control (power saving)
68 C3 FF ; HDMI power control (power saving)
68 C4 FF ; HDMI power control (power saving)
68 C5 00 ; HDMI power control (power saving)
68 C6 00 ; HDMI power control (power saving)
68 C0 FF ; HDMI power control (power saving)
40 0C 40 ; Power up part and power down VDP
40 14 3F ; Disable Tristate of Pins
40 15 80 ; Disable Tristate of Pins
40 19 83 ; LLC DLL adjustment
40 33 43 ; LLC DLL Enable
44 BA 01 ; Set HDMI FreeRun
44 6C 00 ; Use fixed clamp values
4C 00 FF ; Power Down ADC's and there associated clocks
4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
4C B5 00 ; Setting MCLK to 128Fs
68 44 85 ; ADI recommended writes
68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
68 01 00 ; Enable clock terminators
68 0D F4 ; ADI recommended writes
68 14 1F ; Disable compressed Audio Mute Mask
68 3D 10 ; HDMI ADI recommended write
68 44 85 ; TMDS PLL Optimization
68 46 1F ; ADI Recommended Write 
68 60 88 ; TMDS PLL Optimization
68 61 88 ; TMDS PLL Optimization
68 6C 10 ; Disable ISRC clearing bit
68 57 B6 ; TMDS PLL Optimization 
68 58 03 ; TMDS PLL Setting
68 75 10 ; DDC drive strength 
68 85 1F ; ADI Equaliser Setting
68 87 70 ; ADI Equaliser Setting
68 89 04 ; ADI Equaliser Setting
68 8A 1E ; ADI Equaliser Setting
68 8D 04 ; ADI Equaliser Setting
68 8E 1E ; ADI Equaliser Setting
68 90 04 ; ADI Equaliser Setting
68 91 1E ; ADI Equaliser Setting
68 93 04 ; ADI Equaliser Setting
68 94 1E ; ADI Equaliser Setting
68 9D 02 ; ADI Equaliser Setting
68 99 A1 ; HDMI ADI recommended write
68 9B 09 ; HDMI ADI recommended write
68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
72 15 00 ; 444 RGB input
72 16 60 ; RGB 444
72 18 46 ; Disable CSC
72 41 10 ; Power down control
72 49 A8 ; ADI recommended write
72 4C 00 ; 8 bit Output (Set to 0x16 for 12 bit )
72 96 20 ; HPD interrupt clear
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 DE 9C ; ADI Recommended Write
72 BA A0 ; Adjust clock delay
72 D1 FF ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

  • Hi,

      Please ensure with crystal clock 28.63636 MHz, If it is incorrect crystal clock then it may lead
    to Image/Color artifacts issue.

      Also make sure with GND connection by crosschecking with our reference schematic at ez.analog.com/.../7725.ADV7842_5F00_Evaluation_5F00_Board_5F00_Documents.zip

     Kindly note that, Depending on the feature required, the appropriate memory device have to be selected. The memory is required for 3D comb and frame TBC. Memory configuration options for the external SD RAM are provided below,

      

    Note: 64Mb SDR memory module does not allow simultaneous operation of 3D comb or frame TBC.

     

    Thanks,

    Poornima

  • . I am unable to enable time-based-correction, with or without the 3D comb filter enabled. According to the documentation in one of the previous emails, this should be possible with the 256 Mb DDR we are using.

    When I turn on TBC, the image turns solid red, which I assume is a fallback free running mode image. I'm not sure whether TBC is critical for keeping the interlaced fields in sync, but this seemed significant enough to mention.

    Also, here is a sample decoded NTSC video showing the issues we're having, which I stretched vertically from 720x480 to 720x540 to make it 4:3 aspect ratio. I will work on getting you a default resolution sample but need to make some code changes for that.

  • Hi,

       Please let us know, Issue persist only when enabling the TBC & 3D Comb ?

        Also try to configure the memory according to the feature enabled, We have to enable 128MB DDR for "TBC+Comb" feature.

       Kindly note that, It may be useful to use the SW driver at first, then start the AVES2 software and save all of the registers for ADV7842 and ADV7511.

    Thanks,

    Poornima

  • I've been working with the suggestions provided earlier this week. I applied the register settings
    in the previous email, but did not see any improvement.

    To answer a prior question, I have never been able to enable TBC, with or without comb filter enabled. Every time I try it, I get solid red output.

     I also went through our C++ code that assigns the I2C registers and filtered out all of the register settings in the order applied. Since this is extracted from code with some branches, there might be some omissions or settings applied out of order, but I tried to preserve the sequence as best as I could. I marked all of the comments with hashtags.

    I have the settings listed as sequences of three hex values: I2C register, address, and value assigned. In cases where there is a fourth value, this is a mask applied to prevent other values at that particular address from being overwritten. This is also attached.

    It is probably an imperfect representation of the entire sequence, but I hope something will stand out as an obvious error. 

  • Hi,

       Could you try with below register setting & Here some of the register been modified,

       Also Please refer this thread (1) ADV7842  How can I use 3D_Comb (TBC is sttoped) with 64MB SDRAM? - Q&A - Video - EngineerZone Here expert given some suggestion about TBC with 3D comb.

    50 10 05 ; 36 output through AVO1,AV02,DACs
    50 11 08 ; Bus Reversal
    50 19 10 ; ADV7842 Mode
    50 1B 02 ; ADV7511
    40 FF 80 ; I2C reset
    40 F1 90 ; SDP map
    40 F2 94 ; SDPIO map
    40 F3 84 ; AVLINK
    40 F4 80 ; CEC
    40 F5 7C ; INFOFRAME
    40 F8 4C ; AFE
    40 F9 64 ; KSV
    40 FA 6C ; EDID
    40 FB 68 ; HDMI
    40 FD 44 ; CP
    40 FE 48 ; VDP
    50 20 00 ; De-assert HDP
    40 00 01 ; CVBS 4x1 Mode
    40 01 00 ; SD core
    40 03 82 ; 24 bit 422 mode **
    40 04 62 ; Output bus rotation (default)
    40 0C 40 ; Power up Core
    40 15 80 ; Power up pads
    40 19 83 ; LLC DLL phase
    40 33 40 ; LLC DLL enable
    4C 0C 1F ; ADI recommended write
    4C 12 63 ; ADI recommended write
    4C 00 0A ; ADC0 and ADC2 power Up
    4C 02 86 ; Manual Mux enable
    4C 03 A0 ; Manual Mux ADC0
    4C 04 C0 ; Manual Mux ADC2
    94 7A A5 ; Timing Adjustment
    94 7B 8F ; Timing Adjustment
    94 75 0A ; Select 128mb DDR (added)
    94 60 01 ; SDRAM reset
    94 97 00 ; Hsync width Adjustment
    94 B2 60 ; Disable AV codes
    90 00 7F ; Autodetect PAL NTSC SECAM
    90 01 02 ; Pedestal On (ire 7.5)
    90 03 C4 ; Automatic VCR Gain (was Manual VCR Gain Luma 0x40B)
    90 04 0B ; Auto Luma setting
    90 05 C3 ; Manual Chroma setting 0x3FE
    90 06 FE ; Manual Chroma setting
    90 12 09 ; Frame TBC disabled with 3D comb
    90 34 A0 ; Line TBC enabled (added)
    90 A7 00 ; ADI Recommended Write

    Thanks,

    Poornima

  • I ran a few tests over the last few days with these register settings. I had to do my best to insert them into our code in the right place, removing as many conflicting or redundant settings as I could while retaining others that seem to be required for the output to work. It's not as easy as uploading a script - there are lots of branches in our code. Unfortunately, the jittering/line doubling problem persisted.

    I looked up the specs for the DDR we're using for the 3D comb filter, and it looks like it's 256 Mbit, and not 128 Mbit as was specified in the recommend settings. I don't know whether that makes a difference though, as both 128 Mbit and 256 Mbit should support both TBC and 3D-comb.

    I'm thinking the fastest way forward will be to change our code to log the actual register writes with timestamps along with any readbacks that you think might be useful. I think my method of manually following the branches and gathering the sequence of writes was too error prone and didn't provide information about which steps might have gone wrong.

    Also, from our meeting: I was supposed to give you the specs on the proprietary high resolution composite signal found on older GE devices that most of our customers are still using.

    It's 1000 lines per frame, monochrome, and progressive, at 75 Hz. The intended aspect ratio is 1:1, so we would want to decode this to 1000x1000 digital frames.

    The device has a NTSC composite output for this signal as well as the proprietary composite signal.

    Since this is monochrome, I'm wondering whether this could be piped into the green channel for sync-on-green component video if it were configured correctly. I've attempted to plug this into standalone component-to-SDI converters but never got it to sync correctly.

  • Hi,

        Kindly note that, We don't face any jitter issue in our evaluation board while evaluating the NTSC composite signal by enabling the "Frame TBC /3D Comb/I2P" feature.
        Please find our attached UART log for your reference and crosscheck your code against our software driver at HDMISoftware Download Form | Analog Devices
         Also Could you please ensure at your Tx side, For example how you have established the connection between Rx and Tx chip by comparing your schematic against our reference schematic and also check with 'HDMI_RX_PowerSupplies_RevA_050411.pdf' - PCB layout & Power supply design recommendations at (2) ADV7842 Design Support Files - Documents - Video - EngineerZone

    Thanks,

    Poornima