ADV7613: No Video Output on LCD Display

Hi,

 Please let us know whether are you using keyed or non-keyed part and also let us know your source device whether is generator or player?

   ADV7613-P has no HDCP keys.

Hi,

The source device (toradex verdin iMX8mp) is a generator which provides HDMI (Video & Audio) signals to ADV7613. I am using keyed part, below are some register readbacks:

IO MAP:
Addr Data
0x21 0x08
0x6A 0x53
0x6B 0x00
0x6C 0x00
0x6E 0x00
0x6F 0x05
0x83 0x42
0x84 0x00
0x85 0x00
0x87 0x00

HDMI MAP:
Addr Data
0x00 0x00
0x04 0x23
0x05 0xB0
0x0D 0x04
0x51 0x20
0x52 0x7C

I have followed below procedure:
1) Programmed slave mapping addresses
2) Wait for 1ms, then write EDID contents to internal EDID RAM
3) Assert the hot plug (HDMI input) on +5v detect
4) ADI recommended write & custom register settings
5) Enable the LCD display communication

By following above steps HDMI MAP addresses 0x51 & 0x52 are updated which I shown above.

Please let me know if above steps are correct to follow.

Thanks & Regards,
Rupesh Kathar

Hi,

   Please let us know, Are you observing the same issue even with other formats like 1080p ?

   Kindly note that, A video format with a pixel clock of less than 92MHz can be output on a single TX or both TXs (LVDS).
  A video format with a pixel clock of more than 92MHz must be output on both TXs(LVDS).

  For single LVDS link, Please make sure with below register,

Single mode selection : TX_BYPASS_PIX_DEMUX, OpenLDI Tx, Address 0x4E[5]
  

The ADV7613 LVDS transmitter can output a maximum clock frequency of 92 MHz.
1080i/60Hz, the TMDS clock is 74.250MHz and 1080p/30Hz clock rate also would be 74.25Mhz .So we can output with single LVDS link.

Also make sure with below recommended writes configured for LVDS Output.
ADI recommends the below register setting should be programmed to setup the ADV7613 in LVDS mode at ADV7613_Recommended_Settings_Guide.pdf
      C0 43 03 ADI Recommended write
      C0 45 04 ADI Recommended write
      C0 46 53 ADI Recommended write
      C0 47 03 ADI Recommended write

Thanks,

Poornima

Hi,

I am encountering an issue related to TMDS clock frequency and missing clock pulses. Below is the detailed setup and issue description:

TMDS Frequency Calculation:

I have calculated the TMDS frequency based on the TMDSFREQ and TMDSFREQ_FRAC registers, which gives me a TMDS frequency of around 63.59 MHz.
The FREQTOLERANCE is set to the default value of 4 MHz, so I think TMDS frequency is acceptable and is within frequency tolerance range.

Issue Observed:

Despite the calculated frequency being within tolerance, I am seeing the following readbacks from the ADV7613 registers:

NEW_TMDS_FRQ_RAW = 1: This indicates that the TMDS frequency has changed by more than the tolerance set in the FREQTOLERANCE register.
VCLK_CHNG_RAW = 1: This indicates that irregular or missing pulses in the TMDS clock have triggered this interrupt.
HDMI_CONTENT_ENCRYPTED = 0: The input stream processed by the HDMI core is not HDCP encrypted.

Display Configuration:

I am using a single LCD display and only one LVDS transmitter output.
The following registers have been set to suit this setup:
TX_BYPASS_PIX_DEMUX = 1
TX_PIXEL_SWAP = 1

By setting TX_PIXEL_SWAP = 1, the AVI InfoFrame checksum seems correct, and the following registers indicate no errors:
ALWAYS_STORE_INF = 1
AVI_INFO_RAW = 1
AVI_INF_CKS_ERR_RAW = 0

Given these details, I am seeking help to understand the following:

1) What factors could cause the NEW_TMDS_FRQ_RAW = 1 and VCLK_CHNG_RAW = 1 flags to be set, even though the TMDS frequency appears to be within the specified tolerance?
2) What could be the possible root causes of irregular or missing TMDS clock pulses in this setup?
3) What steps or adjustments should I take to resolve this issue?

Any guidance or suggestions would be greatly appreciated.

Thank you for your time and assistance!

Thanks & Regards,

Rupesh

Hi,

  Kindly note that, Pixel clock for '1360x768' is 85.500 Mhz but your case it seems different and it is calculated by using below formula,

     Pixel Clock=Total Horizontal Pixels x Total Vertical Lines x Refresh Rate (Refer VESA document in order to get total horizontal & Vertical pixels)

Also Please check your TMDS freq register calculation against below formula,

At first, Please check with 1080p standard format and let us know about the result.

Thanks,

Poornima

Hi,

I am using pixel resolution 1024 x 768 XGA and pixel clock 65 MHz not 1360 x 768 at 85.5MHz.

Below are the contents of HDMI MAP:
0x51 = 1F
0X52 = CB

I have calculated the TMDS frequency based on the TMDSFREQ and TMDSFREQ_FRAC registers, which gives me a TMDS frequency of around 63.59 MHz.
The FREQTOLERANCE is set to the default value of 4 MHz, so I think TMDS frequency is acceptable and is within frequency tolerance range.

Issue Observed:

Despite the calculated frequency being within tolerance, I am seeing the following readbacks from the ADV7613 registers:

NEW_TMDS_FRQ_RAW = 1: This indicates that the TMDS frequency has changed by more than the tolerance set in the FREQTOLERANCE register.
VCLK_CHNG_RAW = 1: This indicates that irregular or missing pulses in the TMDS clock have triggered this interrupt.
HDMI_CONTENT_ENCRYPTED = 0: The input stream processed by the HDMI core is not HDCP encrypted.

I am seeking help to understand the following:

1) What factors could cause the NEW_TMDS_FRQ_RAW = 1 and VCLK_CHNG_RAW = 1 flags to be set, even though the TMDS frequency appears to be within the specified tolerance?
2) What could be the possible root causes of irregular or missing TMDS clock pulses in this setup?
3) What steps or adjustments should I take to resolve this issue?

Any guidance or suggestions would be greatly appreciated.

Thank you for your time and assistance!

Thanks & Regards,

Rupesh Kathar

Hi,

  Please find the below comments,

1. Poor shielding can introduce noise into the HDMI TMDS signals, causing fluctuations in the clock or signal integrity. Signal degradation due to poor cable quality, long cable lengths, or poor connectors could affect the quality of the TMDS signal, leading to irregularities in the clock frequency or missing pulses.

Hi Poornima,

I have followed the below steps:

1) Disable HPD through HPA_MANUAL or unplugging the HDMI source cable
2) Power up the ADV7613
3) Map slave addresses
4) Load EDID data to ADV7613 through external MCU
5) Load ADI recommended write & custom register settings
6) Enable HPD through HPA_MANUAL or plugging the HDMI source cable
7) Power ON LCD Display

The status of TMDSPLL_LCK_A_RAW[6] (0x6A) is 1, the contents at 0x6A is 0x53, which indicates that incoming clock is perfectly locked with ADV7613.

Also, the source outputs a TMDS clock.

I have provided detailed register writes in my above posts.

Thanks & Regards,
Rupesh Kathar

Hi,

   As stated many times , Please check with 1080p but we didn't get any update regarding that resolution.

  Also make sure with below referred register ,

  If PLL is not detected, then enable the PLL in the OpenLDI transmitter