Hello,
I am using ADV7182A with CVBS input to sample PAL video. I use the following configuration:
dec_write(state, 0x0f, 0x80); //Reset the decoder usleep_range(5000, 10000); dec_write(state, 0x0f, 0x00); //Exit power down mode dec_write(state, 0x52, 0xCD); //SE_CVBS AFE IBIAS, ???, from AD example dec_write(state, 0x00, 0x00); //CVBS in on AIN1 dec_write(state, 0x0E, 0x80); //ADI Required Write dec_write(state, 0x9C, 0x00); //Reset Coarse Clamp Circuitry [step1] dec_write(state, 0x9C, 0xFF); //Reset Coarse Clamp Circuitry [step2] dec_write(state, 0x0E, 0x00); //Enter User Sub Map dec_write(state, 0x17, 0x41); //Select SH1 chroma shaping filter dec_write(state, 0x03, 0x0C); //Enable Pixel & Sync output drivers dec_write(state, 0x04, 0x07); //Power-up INTRQ, HS & VS pads dec_write(state, 0x13, 0x00); //Enable ADV7182 for 28.63636MHz crystal dec_write(state, 0x1D, 0x40); //Enable LLC output driver
I am using a PAL generator with cross hatch pattern to generate small vertical white lines on a black background.
I capture the analog signal with an oscilloscope and note at which time during the horizontal line the pixel of the vertical white line begins.
When I look into the BT.656 data stream, the pixel of the vertical line is 2 to 3 pixel (luma samples) too early.
In my understanding, BT.601-7 clearly specifies the relationship between analog video timing and pixel position.
My question is:
Are there register settings which are influencing the video area in a BT.656 data stream?
Am I missing a configuration step to align analog video signal and BT.656 data stream?
Regards,
Torsten
