adv7391 analog out not working

Hi,

  Could you please do below register configuration for internal test pattern generation and let us know about the result.

    0x00 0x1C
    0x82 0xC9
    0x84 0x40
    0x8C 0xCB
    0x8D 0x8A
    0x8E 0x09
    0x8F 0x2A

For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9 should be written to Subaddress 0x82. For component RGB output rather than YPrPb output, 0 should be written to Subaddress 0x02, Bit 5.

Please refer Page79 and make sure with register configuration as mentioned in section SD TEST PATTERNS of ADV739x datasheet. Kindly note that, 27 MHz clock signal must be applied to the CLKIN pin.

Thanks,

Poornima

Hai PoornimaSubramani ,

Thanks for your reply. We tried setting the test pattern for the SD in the way as like you said. We have got the color bars test pattern with the 27Mhz clock supplied. 

Now our actual requirement is to convert the progressive video to analog. So as according to the video input specifications, we tuned the adv registers as I mentioned

input to the ADV7391 from FPGA is as follows,

Horizontal Active Pixel - 720 px
Horizontal Blank Pixel - 144 px
Vertical Active Line - 576 lines
Vertical Blank Line - 49 lines
Total 625 lines progressive 50 FPS
54 MHz 8 Bit (SAV/EAV Sync)

And the corresponding registers set on the ADV7391 registers are,

i2cset -f -y 0 0x2a 0x17 0x02;
i2cset -f -y 0 0x2a 0x00 0x1C;
i2cset -f -y 0 0x2a 0x01 0x70;    // ED @54Mhz
i2cset -f -y 0 0x2a 0x30 0x1C;     // 625p 50fps
i2cset -f -y 0 0x2a 0x31 0x01;

We have verified and ensured that the pixel clock input to the chip is 54MHz. No luck with this settings. Hope I have configured the chip properly for this input video. Do I missed anything?

PoornimaSubramani ,Please be noted that, I have pasted a wrong image in the query. The actual test pattern from the FPGA looks like the below, 

Only 2.5 gradient bars are there. (The image I posted in the query was different)

Hi,

   Could you please configure 0x01 register as ED-SDR or ED-DDR input mode according to ED configuration table113 and let us know. Then will figure out the issue.

Thanks,

Poornima

Hi PoornimaSubramani 

We didn't see any difference when configured the 0x01 reg as SDR(0x10) or DDR(0x20). The video shown on TV is given below,

Hi,

  ADV7391 output is completely dependent on the input timing So in this case the FPGA would completely control the timing.  If the FPGA outputs the correct timing format then the ADV7391 output will match it with only a small amount of pipeline delay.

Okay PoornimaSubramani  Thanks for the hint. We shall cross verify the video output from the FPGA. 

FYI, as you said we were outputting the static image from FPGA, and the analog out is also static - no rolling or flickering. 

It is shown in the display as 2 sections separated by a black vertical bar in the middle of the screen as shown above. Both sections are vertically stretched and horizontally shrunken. Also some area in the left section is cropped. Next day I shall post the output with a moving pattern as input so that you could get more clarity. BTW, can you re-check and confirm whether the register configurations we have given are right or not? So that we can ensure that the ADV configurations are proper and isolate.

The board production is soon going to start. Need to conclude this case asap.

Thanks. 

Hi,

Hi VarshiniK 

According to the configuration that we have given to the adv7391,

jeevan said:

i2cset -f -y 0 0x2a 0x00 0x1C;

The PLL is ON. We tried disabling it by giving the value 0x1e to the addr 0x00. But no changes observed. 

VarshiniK said:

54 00 1C ; Power up all DAcs and PLL
  54 01 26 ; ED/HD-DDR mode, Y data on DDR rising edge
  54 30 1C ; 625p@50 Frame rate, EAV/SAV codes enabled
  54 31 01 ; HD4X enabled,Pixel data valid
  54 33 6C ; PrPb SSAF , SINC filter enabled, 10 bit input mode enabled
  50 11 00 ; FPGA - DCMs out of reset

When comparing our register configuration with that you provided, only the writes to the addresses 0x01 and 0x33 are found different. I hope the below register write is correct for our case,

jeevan said:

i2cset -f -y 0 0x2a 0x01 0x70;    // ED @54Mhz

Even though we are sure that the video input to the ADV is 8b, we tried setting the other way by writing 0x6C to the addr 0x33. Still no change in the output.

Hi,

  I suspect the issue is with your video source or the EAV/SAV codes being sent.

  What video source are you using and have you verified it directly in to the TV?

  If FPGA then you might not be creating the SAV/EAV bytes correctly or over saturating active video bytes leading to false SAV/EAV signals.

Debugging your FPGA design and the ADV739x functionality at the same time can be difficult. I would suggest that you purchase the accompanying front-end board as well (EVAL-ADV739xFEZ). That would allow you to experiment with ADV739x in a known-good platform.

Thanks,

Varshini K