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HDMI-GR input video selected as VGA but by providing HDMI input, device able to convert RGB888 format.

Category: Software
Product Number: ADV7842

Hi,

HDMI-GR input video selected as VGA but by providing HDMI input, device able to convert RGB888 format.

As per my knowledge HDMI data is digital & VGA is analog.

In HDMI-GR mode I am providing HDMI as input and I am able to generate RGB888. but VGA means analog, still how it is working?

Thanks & Regards,
Mallikarjuna

  • Hi,

       YES VGA is analog interface but we can support any formats over analog or digital interface So we can send graphics format using digital interface(HDMI) and that is the reason we can able to convert RGB888 format.

      Also, By using prime mode register we can able to control Analog-GR and HDMI-GR Mode.

    Thanks,

    Poornima

  • Hi Poornima,

    I am providing HDMI input video with 1024x768 resolution, I want to generate 36bit RGB output, please suggest configuration script file number.

    Thanks & Regards,
    Mallikarjuna.

  • Hi,

      Please refer 1024x768 related configuration (5-3x) at 7725.ADV7842_Evaluation_Board_Documents.zip

     Kindly note that, 0x40 is the main I2C address for the ADV7842.
     '0x72' belongs to main map I2C address for the ADV7511 Tx and you can ignore other writes you are working only with ADV7842.
    Thanks,
    Poornima
  • Hi,

    I am providing HDMI input video but in below script HDMi registers are not configured.

    ##Scripts 5 CP Graphics XGA-##
    :5-3a 1024x768@60 XGA RGB in_ 444 24bit H_V_DE DAC:
    50 10 01 ; Data to DAC only
    50 19 10 ; ADV7842 Mode
    50 1B 02 ; ADV7511
    40 FF 80 ; I2C reset
    40 F1 90 ; SDP map
    40 F2 94 ; SDPIO map
    40 F3 84 ; AVLINK
    40 F4 80 ; CEC
    40 F5 7C ; INFOFRAME
    40 F8 4C ; AFE
    40 F9 64 ; KSV
    40 FA 6C ; EDID
    40 FB 68 ; HDMI
    40 FD 44 ; CP
    40 FE 48 ; VDP
    40 00 0C ; VID_STD=01100b for XGA60
    40 01 82 ; Prim_Mode to graphics input
    40 02 F6 ; Auto input color space, Limited Range RGB Output
    40 03 42 ; 24 bit SDR 444
    40 05 28 ; Disable AV Codes
    40 0C 40 ; Power up Part
    40 15 B0 ; Disable Tristate of Pins except for Audio pins
    44 73 EA ; Set manual gain of 0x2A8
    44 74 8A ; Set manual gain of 0x2A8
    44 75 A2 ; Set manual gain of 0x2A8
    44 76 A8 ; Set manual gain of 0x2A8
    44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
    44 C3 39 ; ADI recommended write
    4C 0C 1F ; ADI recommended write
    4C 12 63 ; ADI recommended write
    4C 00 80 ; ADC power Up
    4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
    4C C8 25 ; DLL_PHASE - 100101b
    End

    Thanks & Regards,
    Mallikarjuna

  • Hi,

      Please use below configuration and configure "40 00 0C" VID_STD=01100b for XGA60.

    50 10 01 ; 36 output through DACs
    50 19 10 ; ADV7842 Mode
    50 1B 02 ; ADV7511
    50 20 00 ; De-assert HDP
    40 FF 80 ; I2C reset
    40 F1 90 ; SDP map
    40 F2 94 ; SDPIO map
    40 F3 84 ; AVLINK
    40 F4 80 ; CEC
    40 F5 7C ; INFOFRAME
    40 F8 4C ; AFE
    40 F9 64 ; KSV
    40 FA 6C ; EDID
    40 FB 68 ; HDMI
    40 FD 44 ; CP
    40 FE 48 ; VDP
    40 01 06 ; Prim_Mode =110b HDMI-GR
    40 02 F6 ; Auto input color space, Limited Range RGB Output
    40 03 42 ; 36 bit SDR 444 Mode 0
    40 05 28 ; AV Codes Off
    68 C1 FF ; HDMI power control (power saving)
    68 C2 FF ; HDMI power control (power saving)
    68 C3 FF ; HDMI power control (power saving)
    68 C4 FF ; HDMI power control (power saving)
    68 C5 00 ; HDMI power control (power saving)
    68 C6 00 ; HDMI power control (power saving)
    68 C0 FF ; HDMI power control (power saving)
    40 0C 40 ; Power up part and power down VDP
    40 15 80 ; Disable Tristate of Pins
    40 19 83 ; LLC DLL phase
    40 33 40 ; LLC DLL enable
    44 BA 01 ; Set HDMI FreeRun
    44 3E 00 ; Disable CP Pregain Block
    44 6C 00 ; Use fixed clamp values
    4C 00 FF ; Power Down ADC's and there associated clocks
    4C 01 FE ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer
    4C B5 01 ; Setting MCLK to 256Fs
    68 00 32 ; Set HDMI Input Port A (Enable BG monitoring)
    68 01 18 ; Enable clock terminators
    68 0D 34 ; ADI recommended write          
    68 1A 8A ; Unmute audio
    68 3D 10 ; HDMI ADI recommended write
    68 44 85 ; TMDS PLL Optimization
    68 46 1F ; ADI Recommended Write ES3/Final silicon
    68 60 88 ; TMDS PLL Optimization
    68 61 88 ; TMDS PLL Optimization
    68 6C 18 ; Disable ISRC clearing bit, Improve robustness
    68 57 B6 ; TMDS PLL Optimization
    68 58 03 ; TMDS PLL Setting
    68 75 10 ; DDC drive strength
    68 85 1F ; ADI Equaliser Setting
    68 87 70 ; HDMI Recommended write
    68 89 04 ; ADI Equaliser Setting
    68 8A 1E ; ADI Equaliser Setting
    68 93 04 ; ADI Equaliser Setting
    68 94 1E ; ADI Equaliser Setting
    68 9D 02 ; ADI Equaliser Setting
    68 99 A1 ; HDMI ADI recommended write
    68 9B 09 ; HDMI ADI recommended write
    68 C9 01 ; HDMI free Run based on PRIM_MODE, VID _STD
    Thanks,
    Poornima
  • Hi,

    44 BA 01 ; Set HDMI FreeRun, FreeRun means it will not consider external HDMI input, for considering external HDMI input this register need to configure with 0, is my understanding is correct or not.

    Thanks & Regads,
    Mallikarjuna.

  • Hi,

    The 7842 will always output what it see at the input, if there is no input then it will free run per the VID_STD if free run enabled.

     HDMI free run mode 0: free run is triggered when the TMDS clock is not detected, for example, in a cable disconnect situation.
      HDMI free run mode 1: free run is triggered when the TMDS clock is not detected or when the detected input format does not match the format dictated by the PRIM_MODE and VID_STD settings.

    Thanks,

    Varshini K