Post Go back to editing

decode a pal video 720 x 576 input abnormal

Category: Datasheet/Specs
Product Number: ADV7182A

ADV7182 is applied to decode a pal input with 720 x 576 resolution, there is a absence around 20 pixels on the right of display 

when is use the internal test video. this abnormal case doesn't exist.

I want to know which registers can deal with this case??

first picture is internal test video, it looks normal 

 

the second picture is the decoding result of 720 x 576 input. it look a absence around 20 pixel on the right 

the picture third: following register is initiated on the power, other registers is default.

  • Hi,

      Some of your register configuration seems different from the reference one So please use configuration according to our reference script and let us know the result.

    42 17 41; Enable SH1
    42 52 CD; SE_CVBS AFE IBIAS
    42 04 07; Power-up INTRQ, HS & VS pads

    By default, the ADV718x video decoders receive analog video and output digital video in accordance with the ITU-R BT.656-3 standard.
    If the receiver system is expecting an ITU-R BT.656-4 output from the ADV718x then this can result in 10 lines of black video being output at the screen.

    Thanks,

    Poornima

  • Hi Poornnima,

    thanks for your reply

    i do the test after modify three register:

    reg[17] = 0x41

    reg[52] = 0xcd

    reg[04] = 0x07 or reg[04] = 0x87  

    "If the receiver system is expecting an ITU-R BT.656-4 output from the ADV718x then this can result in 10 lines of black video being output at the screen", according to the reg4.bit7 description(set reg[04] = 0x07 or reg[04] = 0x87 ), but the result is same, there is no obvious difference

    follow list the all register :

    by the way, 

    42 17 41; Enable SH1
    42 52 CD; SE_CVBS AFE IBIAS
    42 04 07; Power-up INTRQ, HS & VS pads

    what is the mean of number '42' above.  sorry, i am not familiar with the datasheet

  • another question:

    when i change main map register 31 34 35 to adjust HSB HSE parameters ,the display looks does't work

    Is it necessary to config other register make this parameters valid ?

    Thanks

  • Hi,

     Kindly make sure with crystal clock (i.e) you are providing correct XTAL 28.6363,and your script selects 28.63636 crystal.

     Normally sinks would expect the correct timing. It depends on how the sink interprets the incoming timing.  If the sink thinks the Hsync back porch is only 10 pixels wide and the source is outputting a back porch of 100 pixels then we will get a 90 pixel black bar on the left side of the screen.

    So we need to look at the timing on a scope and try to match it to a timing the sink is expecting.
    Please note that ADV7180 has no memory and can't retime the signals-- it can't add or remove lines.  If 10 lines were actually lost then the pixel clock should be different as well as the H sync.
    Also ADV7180 does not use frame memory, so an image cannot be stored. If there are issues with the output timing/ alignment, the image would have some black (non-active) video on the left or right.

    '0x42' belong to IO map address of ADV7180. By using this address we can access all ADV7180 IN/OUT related registers.
     
    Thanks,
    Poornima