Enabling PLL stop video conversion to CVBS

Hi,

 Please ensure with below 16x PLL configuration been enabled for SD mode since this setting multiplies the input clock frequency by 16, which is typically used for standard definition (SD) video formats.

 As per our default configuration, enable 0x00 register value as 0x1C - All DAC enabled/ PLL enabled(16x) and let us know about the result.

Thanks,

Poornima

PLL does not work. I tried next steps:

root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x17 0x02 # Software reset.
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x82 0xC3 # SD PrPb SSAF filter + SD DAC Output 1 (Enable CVBS) + Data Valid
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x88 0x10 # 10-bit input enabled.
## At this moment I can see the video 

## After each  of the next commands I do not see the video
## I tried them one by one and at any step the video was not converted, the screen was black
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x00 0x10 # PPL + DAC1
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x00 0x1C # PPL + all DAC
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x0D 0x0E
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x0D 0x06
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x0D 0x00
root@j721s2-evm:/opt/edgeai-gst-apps# i2cset -y 1 0x2a 0x0D 0x08

##Disable PPL and  I see the video again
i2cset -y 1 0x2a 0x00 0x12 # no PPL + DAC1

Hi,

  Kindly note that, for PAL operation an input clock of 29.5 MHz is required. If disabling the PLL solves your problem means, It indicates that the components used in the loop filter circuit need to be changed.
   You do need the correct loop filter components for the PLL. You can use a 169 1% resistor instead of 170 Ohms
The loop filter requires these parts only.
For the caps, It is suggested to use 150nF and 12nF 10% 25-50V NPO(C0G)
For the resistor, It is suggested to use 169 Ohm 1%.

If you are using the full temperature range, We would recommend using COG capacitors for their superior temperature performance.

We do recommend the tight tolerances for the loop filter components to ensure the stability of the PLL.

Hi,

For reference, below you can see the schematic of how the chip is connected on our side.   

For the caps, we use 150nF and 10nF. Is it a problem that we use 10nF instead of 12nF? 
Could you also check if there is no problems with the connections in the schematic picture provided? 

Regarding the clock:

We provide a 27MHz clock as required for standard ITU-R BT.601/656 with a video resolution of 720x480.

Also please note, that we provide ITU-R BT.601/656 video, but the register 0x80 is set to default value 0x10, meaning NTSC.

Let me know if you need any additional information.

Best regards,
FoxFour

Hi,

  Kindly note that, When capacitance decreases from 12nf to 10nf then cut-off frequency of a External loop filter also decreases So use the filter components as per expert suggestion.

  Please crosscheck your schematic against our reference one at      6428.ADV739x_Evaluation_Board_Documents.zip

 By default, 0x80 register value is '0x10' If you are using PAL then configure that register as '0x11'.

Hi,

We tried to change to a 10nF capacitor but it did not help to enable PLL.
The schematic looks good according to your reference.

"Please crosscheck your schematic against our reference"
We use NTSC

Best regards,
FoxFour

Hi,

The ADV739x PLL only provides the oversampling clock.  Other then this the output is strictly based on your 27MHz incoming clock.

on the ADV739x output, is the color burst stable and the right amplitude.

 can you attach a ntsc image with color problems?

For ADV7393 are the EXT_LF components close to the part and the reference PVDD_1.8V supply very clean, especially when running ntsc?

Normally these issues are related to poor color burst qualities and/or instability in the final NTSC signal.

Thanks,

Varshini K