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Does the Free Run not work in non standard mode?

Category: Datasheet/Specs
Product Number: ADV7403

I'm using ADV7403 in non-standard mode. The problem is that when the input cable is not connected, the free-run mode screen doesn't work. The CP_FREE_RUN bit of STATUS Register2 is '1', but the output is nothing. Refer to the setting below.

42 05 01 ;
42 06 0C ;
42 1D 47 ;
42 3A 11 ;
42 3B 80 ;
42 3C 5C ;
42 6A 10 ;
42 6B C0 ;
42 6C C3 ;
42 6D 00 ;
42 6E 80 ;
42 6F 08 ;
42 70 00 ;
42 71 69 ;
42 72 5f ;
42 73 D0 ;
42 74 04 ;
42 75 01 ;
42 76 00 ;
42 77 84 ;
42 78 08 ;
42 79 02 ;
42 7A 00 ;
42 7B 10 ;
42 7c 40 ;
42 86 0B ;
42 87 E4 ;
42 88 e6 ;
42 8A B0 ;
42 8F 04 ;
42 90 43 ;
42 C3 31 ;
42 C4 C2 ;
42 0E 80 ;
42 52 46 ;
42 54 00 ;
42 0E 00 ;
54 00 13 ; Power down Encoder
74 EE EE ; Power down HDMI
End

  • Hi,

      Could you please enable below configuration from your end and let us know about the free run output,

    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 00 ; Blue Screen Free Run Colour
    42 C1 87 ; Blue Screen Free Run Colour
    42 C2 00 ; Blue Screen Free Run Colour

    If above configuration doesn't work then try to force free run by the enabling 0th bit in 0xBF register (42 BF 07).

    Thanks,

    Poornima

  • Thank you for your answer.

    I tried to set those values, but it's not working. The monitor just displays 'no signal'. 

  • Hi,

      Kindly let us know, This 'no signal' output is occurring only with non standard format or even with standard one ?

    Please force the free run in SDP mode by configuring below register.

        0x0C (DEF_ VAL_ EN) register(42 0C 37) is used to force free run mode in SDP mode.

     Also check with below configuration and let us know,

    42 05 01 ; Prim_Mode =001b COMP
    42 06 08 ; VID_STD=1000b for 525P 2x2
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
    42 3B 80 ; Enable External Bias
    42 3C 53 ; PLL_QPUMP to 011b
    42 6B 80 ; Enable DE output, swap colours
    42 73 F0 ; Enable Manual Gain and set CH_A gain
    42 74 0C ; Set CH_A and CH_B Gain
    42 75 03 ; Set CH_B and CH_C Gain
    42 76 00 ; Set CH_C gain
    42 77 04 ; Set offset to 64d
    42 78 01 ; Set offset to 64d
    42 79 00 ; Set offset to 64d
    42 7A 40 ; Set offset to 64d
    42 7B 1D ; TURN OFF EAV & SAV CODES Set BLANK_RGB_SEL
    42 85 19 ;Turn off SSPD and force SOY. For Eval Board.
    42 86 0B ; Enable stdi_line_count_mode
    42 BF 06 ; Blue Screen Free Run Colour
    42 C0 00 ; Blue Screen Free Run Colour
    42 C1 87 ; Blue Screen Free Run Colour
    42 C2 00 ; Blue Screen Free Run Colour
    42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting

    Thanks,

    Poornima

  • Only non-standard get "no signal". I tested the 1080i/60Hz on the same hardware configuration, which was fine.

    Thanks,

  • Hi,

      Please configure "FR_LL" register value as '0x00' but in your shared configuration seems you have been set 'FR_LL' register as "42 8F 04" & "42 90 43" ;

      Kindly note that "FR_LL" parameter holds the ideal line length for a given video standard. It affects the way CP handles the unlocked state.

    If set to 0, the internally used free-run line length value is decoded from the current setting of PRIM_MODE and VID_STD. For standards not covered by the preprogrammed values, the FR_LL[10:0] parameter must be set to the ideally expected length of one line of input video.

    Thanks,

    Poornima

  • I calculated the FR_LL value based on 'Nonstandard_Video_Formats_17_Sept_08.pdf'. And, if FR_LL is set to '0' or another value, the monitor does not output at all even when the input is connected.

    So my question again is, 'Does free-run mode work properly when operating in non-standard mode?'

    Thanks,

  • Hi,

      Please check the same in our evaluation board.

      Kindly note that, I don't think we faced such free run issue in our evaluation board in non-standard mode.

    Thanks,

    Poornima

  • Hi,

    I already tested it on your ADV7403 EV board. The result is the same thing. And I also had the same result with 'RGB  1078x809 _@ 30 ADV7404  34.650MHz Out through DAC:' in your setup files( 'ADV7403_ADV7403@_ADV7341-VER.1.3.txt;) on EV board. I think that the 'RGB  1078x809 _@ 30' setting is a non-standard mode.

    Thanks,

  • Hi,

       Kindly make sure with FR_LL calculation, It should work if we have configured in a right way for non standard mode.

          

      To configure the CP for nonstandard video, the FR_LL[11:0] must be set manually. This enables it to ignore the default line length associated with the corresponding VID_STD[3:0]. To calculate the FR_LL[11:0] manual parameter, the line period is divided by the 27 MHz clock period .

    In Non-standard vid modes you may need to adjust clamp, Kindly refer to page 71 of ADV7403_Manual (Clamp Operation (CP) section)..

    To check it ->

    1. with video signal on input try following:

       - run your script

       - make sure picture is stable

       - use CLMP_FREEZE

    If you see that after freezing clamp picture is ok for a 2-3 seconds, then it dims - it means that clamps need adjusting by using registers CLMP_X_MAN and CLMP_X.

     WHERE x = A, B, C; If after using mentioned register there is no short-time improvement

     It means that this is not a clamp-related issue.

    Please check below PLL and FR_LL related configuration for 1024x768 resolution and configure according to your format which are highlighted in blue color.

    42 05 02 ; Prim_Mode =010b for GR
    42 06 0C ; VID_STD=1100b for 1024x768 _@ 60
    42 1D 47 ; Enable 28MHz Crystal
    42 3A 21 ; set latch clock settings to 010b, Power Down ADC3
    42 3B 80 ; Enable External Bias
    42 3C 5D ; PLL_QPUMP to 101b
    42 6A 00 ; DLL Phase Adjust
    42 6B C2 ; Swap Pr & Pb
    42 73 90 ; Set man_gain
    42 7B 1D ; TURN OFF EAV & SAV CODES Set BLANK_RGB_SEL
    42 85 03 ; Enable DS_OUT
    42 86 0B ; Enable stdi_line_count_mode
    42 87 E4 ; Man set PLL_DIV_RATIO to number of pixels per line
    42 88 F0 ; Man set PLL_DIV_RATIO to number of pixels per line
    42 8F 02 ; FREE_LL = period of line / period of XTAL
    42 90 F8 ; FREE_LL = period of line / period of XTAL
    42 F4 3F ; Max Drive Strength
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 0E 00 ; ADI Recommended Setting

    Please note that Analog Devices provides this Application Note only at http://www.analog.com/static/imported-files/application_notes/AN-0978.pdfWe don’t have sources for all nonstandard video modes. 

    Thanks,

    Poornima

  • HI,

    Thank you for your answer. However, your PLL_DIV_RATIO and FREE_LL are not working.  These values can't make a screen on the monitor when the cable is connected or disconnected. You can see the values I'm using below the line.

    Frequency of Pixel clock: 32.9175 MHz

    Frequency of Horizontal sync: 26.25 KHz

    P.S.: I think the value you sent me is for 1024x768@43.

    Thanks,