Category: Hardware
Product Number: ADV7403
We are using an ADV7403 as an RGsB decoder and seeing problems at cold. There are no observed problems between temperatures of approximately 0 C and 70C, but there appear to be LLC1 synchronization issues at temperatures between approximately -40C and -20C.
The ADV7403 receives an RGsB input and drives a 30-bit RGB decoded output to a Xilinx Artix-7 FPGA.
In the failed state the video initially seems to have severe sync issues. As the system warms up the quality of the video improves, but is still failing; it is jittery, fuzzy, and every other line often appears offset as though there's an interlacing alignment issue although the video is progressive. We have an input statistics module in the FPGA that measures ADV7403 parallel video timing periods and LLC1 clock frequency. When things are operating correctly we read the following statistics:
Total horizontal pixels: 1056
Active horizontal pixels: 800
Total vertical lines: 628
Total pixel clock cycles per frame: 663,168
Pixel clock frequency: 40.00025 MHz
When failing, the pixel clock frequency appears slightly lower and the video timing parameters are not stable. Example parameters during a failure are below. This data was captured when the loss of sync is not the most severe, but does show jitter, every other line issues, fuzziness, etc.
Total horizontal pixels: 1055-1057
Active horizontal pixels: 791-801
Total vertical lines: 625-629
Total pixel clock cycles per frame: 660,001-664,223
Pixel clock frequency: 39.93926 MHz
The video input is progressive scan RGsB 800x600 at 60 Hz. The video is generated as VGA by a StarTech USB2VGAE3 and is then converted from VGA to RGsB by a Magenta Research 4002910-01. A scope capture of the input video is attached. Note that the scope capture was taken using a "T" with 50 Ohm cable to scope. All cabling in the system test setup is 75 Ohms.
Attached are:
* ADV7403 schematic
* Register initialization SW sequence
* Input video screen capture
* FPGA input setup and hold timing report
Troubleshooting efforts to date:
* Tried changing ADC drive strength from Medium Low to High
* Tried changing ADC reference clock from 28.636363 MHz to 27 MHz (27 MHz can be generated in FPGA w/ nominal 150 ps pk-pk jitter instead of 350 ps pk-pk for 28.636363 MHz)
* Replaced the following ferrite beads with zero ohm resistors: FB5, FB16, FB14, FB3, FB20, FB1, FB2, FB4
* Measured ADC voltage supply noise using on-board power supply monitoring ADC. At cold during failure PVDD noise is 18 mVpk-pk, AVDD noise level is 24 mVpk-pk. AVDD and PVDD noise levels are only slightly higher at cold. DVDD noise levels are approximately 30% higher at cold.
* Monitored various lock signals in the ADV7403 register space, but have not been able to find any lock-related status bits that indicate loss of lock while the issue is occurring. Disconnecting the video input does produce a loss of lock indication, but during this failure mode there does not appear to be any loss of lock indicated.
* Captured input video signal to make sure that sync level was appropriate. Sync tip is approximately 260 mV. Input video signal is outside of thermal chamber and does not change during temperature testing.
