[ADV7480] Behavior when HDMI cable is unplugged with Free Run disabled setting

Hi,

When free run is prohibited, please tell me the expected behavior of ADV7480 when the HDMI cable is unplugged.

Please contact us if there is any information that needs to be confirmed with the customer.

Best regards.

Hello,

I get your point cp_free_run status bit seems not to show the part is free running. But free run is only disable in one of the two controls:
　(E0 03 Bit1) I2C FREE RUN EN=0 (Disable CP free run mode)
　(E0 04 Bit7) i2c cp force freerun ch1=0 --> This setting is default CP free runs automatically

Free run can be forced by the cp_force_freerun_ch1 control or by the cp_force_freerun control:
cp_force_freerun (default = 0: Do not force CP core free run)
cp_force_freerun_ch1 (default = 0: CP free runs automatically)

def_val_en (default = 0: Free-run mode dependent on DEF_VAL_AUTO_EN) --> What is the setting here?
free_run_pat_sel[2:0] (default = 000: Single color set by DEF_Y/DEF_C controls) --> What is the setting here?

hdmi_frun_en (default = 1: Enable free run feature in HDMI/MHL mode) --> What is the setting here?
There are two free run modes in HDMI/MHL input mode:
hdmi_frun_mode (default = 0: HDMI/MHL free run mode 0. Part free runs when TMDS clock not detected on selected HDMI/MHL port) --> What is the setting here?

Can you please check cp_force_freerun_ch1 again? But I would agree it seems to be odd cp_free_run status bit is not set in the case of free run.

Hi,
Thank you for contacting us. We will check with the customer about the register values.

Customer is using a setting that disables free run.

When free run disabled, what state will ADV7480 output(MIPI output) be in if the HDMI cable is unplugged while video is being output?
　Hi-z? LP00 LP11 Other?
When free run disabled, please tell us the expected behavior of ADV7480 when the HDMI cable is unplugged.

Best regards.

Hi,

  When free run disabled, what state will ADV7480 output(MIPI output) be in if the HDMI cable is unplugged while video is being output ?

  The outputs will not immediately go into LP state from HS until the transmitter will finish out the current video line.

Note: The users can power down the part by setting /PWDN low (clock is LP-00 state), then power up the part again by setting /PWDN high (the clock state is LP-11).  Setting /PWDN low then high will get the CSI clock in PL-11-state. Please make sure that there is no received data when doing this.

Thanks,

Poornima

Hi,

  Also note that, If free run is disabled and there is no input then the outputs may show the default clocking (By default, the clock output(CLKAP, CLKAN) is held in a zero state) or what the last frequencies the PLLs were locked to.  

  From a code stand point is you lose TMDS frequency detect, then you can tri-state the output port.  This will stop the clocking.   When TMDS frequency detect goes high & you can re-enable the outputs.

  There has been no report by customers using the ADV748x of any issue caused by any transient in the video output between the moment the HDMI cable gets disconnected.

Thanks,

Poornima