Not Getting the expected bar pattern output on pixel format

Hi,

  Above shared configuration seems different from reference one So please crosscheck your configuration against "##CP YPrPb 525i & 625i## :625I YPrPb In 12Bit RGB DDR HS/VS HDMI:" at 6545.ADV7181D_Evaluation_Software.zip

Thanks,

Poornima

Hi Poornima 

Thanks for the response!! 

Now we are getting all the colours we are sending from the TX side 

I have one more query

When we haven't connected any cable, we are still getting sync on the pixel output side. we want that it should not generate any junk pixel data and sync when the cable is not connected. So can you please help us to find which register is causing it and what need be configured on that register to generate to stop junc pixel and sync data generation. 


An early response will be highly appreciated!
 

Hi,

If free run is disabled and there is no input or Cable disconnected then the outputs may show the default clocking or what the last frequencies the PLLs were locked to.  

 From a code stand point is you lose TMDS frequency detect, then you can tri-state the output port.  This will stop the clocking.   When TMDS frequency detect goes high & you can re-enable the outputs.

Thanks,

Poornima

Hi Purnima 

Thanks for the quick response !! 

Can you please tell the register which tell when we have lost the TMDS frequency detect. 

Also there is one more query that when we are sending a fixed bar pattern from the DAC side to ADC side we are getting correct vsync from the digital output side of ADC but when we change the pattern to moving bar pattern we are getting the vsync shifted by half a line after moving bar pattern is moved by 4 bars. We are operating on Sync on green in configuration. So can you help us to debug this issue. 

An early response is highly appreciated !!

Hi,

Did you probe the HS, VS and DE signals versus the data signals at the output of the ADV7181D with an oscilloscope? Do you see the shift at the output of the ADV7181D? Did you check if the shift is occurring in the backend device(s)?

You could try adjusting the following controls to see if they can fix your problem:

START_HS[9:0] - Address 0x7C and 0x7E, [3:2] and [7:0]

END_HS[9:0] - Address 0x7C and Address 0x7D, [1:0] and [7:0]

START_VS[3:0] - Address 0x7F, [3:0]

END_VS[3:0] - Address 0x7F, [7:4]

START_FE[3:0] (Start Field Even) - Address 0x80, [7:4]

START_FO[3:0] (Start Field Odd) - Address 0x80, [3:0]

 PIN_IN_HS - Address 0x7C, [7]

PIN_INV_VS - Address 0x7C, [6]

PIN_INV_F - Address 0x7C, [5]

I advise that the customer monitor the IN_LOCK and FSC_LOCK bits. IN_LOCK shows if the ADV718x has locked to the horizontal sync. FSC_LOCK shows if the ADV718x has locked to the color subcarrier frequency. 

Thanks,

Varshini K