Post Go back to editing

Unable to any video output from ADV7280A-M

Category: Software
Product Number: ADV7280A

Hi, 

We are using EVAL-ADV7280AMEBZ with iMX8M Mini (L6.1.55 mickledore), and unable to get any video output or even color bars test pattern on display via gstreamer.

Please see the DT entry below:

diff --git a/imx8mm-test.dtsi.orig b/imx8mm-test.dtsi
index 8067e4d..6a43567 100644
--- a/imx8mm-test.dtsi.orig
+++ b/imx8mm-test.dtsi
@@ -479,36 +479,44 @@
 		dsd-path = <1>;
 	};
 
-	ov5640_mipi: ov5640_mipi@3c {
-		compatible = "ovti,ov5640_mipi";
-		reg = <0x3c>;
-		status = "okay";
+	adv7280_mipi1: adv7280_mipi1@21 {
+        status = "okay";
+        compatible = "adi,adv7280-m";
+        reg = <0x21>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
+		pinctrl-0 = <&pinctrl_adv7280>;
+		powerdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 
+		reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "adv7280m_intrq";
+		adv,force-bt656-4 = <1>;
 		clocks = <&clk IMX8MM_CLK_CLKO1>;
 		clock-names = "csi_mclk";
 		assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
-		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
-		assigned-clock-rates = <24000000>;
+        assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
+        assigned-clock-rates = <24000000>;
 		csi_id = <0>;
-		pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
-		mclk = <24000000>;
-		mclk_source = <0>;
-		port {
-			ov5640_mipi1_ep: endpoint {
-				remote-endpoint = <&mipi1_sensor_ep>;
-			};
+        mclk = <24000000>;
+        mclk_source = <0>;
+        port {
+            adv7280_mipi1_ep: endpoint {
+                remote-endpoint = <&mipi1_sensor_ep>;
+                clock-lanes = <1>;
+                data-lanes = <1>;
+            };
 		};
 	};
+	

 	};
 
 	
@@ -524,11 +532,13 @@
 	status = "okay";
 	port {
 		mipi1_sensor_ep: endpoint@1 {
-			remote-endpoint = <&ov5640_mipi1_ep>;
-			data-lanes = <2>;
+			remote-endpoint = <&adv7280_mipi1_ep>;
+			clock-lanes = <1>;
+			data-lanes = <1>;
 			csis-hs-settle = <13>;
 			csis-clk-settle = <2>;
 			csis-wclk;
+			bus-width = <1>;
 		};
 
 		csi1_mipi_ep: endpoint@2 {
@@ -784,15 +794,16 @@
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x000
 			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23       0x140  //int
-			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19 //rst
+			/*MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19 //rst*/
 			
 		>;
 	};
 
-    pinctrl_tch_ts: tchgrp {
+    pinctrl_adv7280: adv7280grp {
 			fsl,pins = < 
-			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19  //INT - P40 
-			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19  //RST - P38
+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x140 /* PDN - P40 */
+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /*  RST - P38*/
+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x140 /* INT - P37 */
  		>;
  	};
  		


Drivers used:
1. drivers/media/i2c/adv7180.c
2. drivers/media/platform/mxc/capture/mxc_mipi_csi.c
3. drivers/media/platform/mxc/capture/mx6s_capture.c

Initially, theUYVY pixel format is not supported by mxc_mipi_csi.c so we added patch to add support for it:
diff --git a/mxc_mipi_csi.c.orig b/mxc_mipi_csi.c
index ed111e9..b620848 100644
--- a/mxc_mipi_csi.c.orig
+++ b/mxc_mipi_csi.c
@@ -318,6 +318,10 @@ static const struct csis_pix_format mipi_csis_formats[] = {
 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
 		.data_alignment = 16,
 	}, {
+		.code = MEDIA_BUS_FMT_UYVY8_2X8,
+		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
+		.data_alignment = 16,
+ 	} , {
 		.code = MEDIA_BUS_FMT_SBGGR8_1X8,
 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
 		.data_alignment = 8,
@@ -343,10 +347,15 @@ static inline struct csi_state
 static const struct csis_pix_format *find_csis_format(u32 code)
 {
 	int i;
-
+	printk(" \n Finding MIPI_CSI Format Code: %d, from formats arr: %ld \n", code, ARRAY_SIZE(mipi_csis_formats));
 	for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
+	{
 		if (code == mipi_csis_formats[i].code)
+		{
 			return &mipi_csis_formats[i];
+		}
+	}
 	return NULL;
 }
 


To set i2p conversion, we also added patch at adv7180.c modifying:

@@ -1410,7 +1494,10 @@ static int adv7180_probe(struct i2c_client *client,
return -ENOMEM;
state->client = client;

- state->field = V4L2_FIELD_ALTERNATE;
+ state->field = V4L2_FIELD_NONE;


Attached also are logs for reference including debug logs for each driver:
progressive_test.log

From the logs, the adv7280 was probed successfully and can be communicated via i2c.

Color bars are generated via DVP Eval software, after setting the color bars to 480p, below are the register dump:



Probed some of the signals using AN1337 as reference:, and signals looking good.
CSI CLK @ 218 Mhz on the oscilloscope as we're using progressive output and captured signals on the data lines too


Other things we have tried is from other posts in the forum by adding in adv7180.c:

@@ -879,6 +956,11 @@ static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
{
struct adv7180_state *state = to_state(sd);
int ret;

+ adv7180_csi_write(state, 0x00, 0x80);
+ adv7180_csi_write(state, 0x00, 0x00);

/* It's always safe to stop streaming, no need to take the lock */
if (!enable) {





AN1330 to AN1337
[edited by: Disen at 7:22 AM (GMT -4) on 17 Jul 2024]
Parents
  • Hi,

      At first, Please crosscheck your schematic with reference one and check clock coming out from our chip at (+) ADV7282 and ADV7282-M Design Support Files - Documents - Video - EngineerZone (analog.com)

      Also make sure with IMX6 MIPI-CSI2 is configured to match the MIPI clock rate of the ADV7280-M.

      As part of MIPI specification, the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. High speed, Low power mode etc.). The receiver needs to detect the mode of operation and dynamically set its termination accordingly. Note that the Clock signals will only appear correctly when properly terminated.
     When we try to terminate the output signals from the ADV7280-M (Microprocessor / FPGA) then you will see the correct MIPI traces.
     Note that the Microprocessor / FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the Micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.
     Please ensure your MIPI receiver (Microprocessor/ FPGA) has been configured correctly.
    This is described in applications note AN-1337
    For our evaluation of the ADV7280-M we used the MIPI reference termination board which is available from here:

    Thanks,

    Poornima

Reply
  • Hi,

      At first, Please crosscheck your schematic with reference one and check clock coming out from our chip at (+) ADV7282 and ADV7282-M Design Support Files - Documents - Video - EngineerZone (analog.com)

      Also make sure with IMX6 MIPI-CSI2 is configured to match the MIPI clock rate of the ADV7280-M.

      As part of MIPI specification, the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. High speed, Low power mode etc.). The receiver needs to detect the mode of operation and dynamically set its termination accordingly. Note that the Clock signals will only appear correctly when properly terminated.
     When we try to terminate the output signals from the ADV7280-M (Microprocessor / FPGA) then you will see the correct MIPI traces.
     Note that the Microprocessor / FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the Micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.
     Please ensure your MIPI receiver (Microprocessor/ FPGA) has been configured correctly.
    This is described in applications note AN-1337
    For our evaluation of the ADV7280-M we used the MIPI reference termination board which is available from here:

    Thanks,

    Poornima

Children
No Data