Questions regarding behavior of LRCK clock after POR

Hi,

Please refer HDMI 14b specification, Section” Audio” to know more details about Audio clock regeneration. The recommended N and expected CTS values for several standard TMDS clock rates are listed down in Table 7.1, 7.2 and 7.3.

The N/CTS parameters used for regeneration of audio clock vary when you change input or timing.

First you must get the TMDS PLL lock bit to lock up. Without this, nothing will work. I'd start by checking the TMDS clock lines with a scope to see if the are the correct amplitude and frequency at the ADV7611 input.

What is the cable like between the ADV7611 and the source?

Probe the TMDS clock lines with a scope. If the ADV7610 is enabled and set up correctly and the TMDS clock lines are stable, right frequency and amplitude/offset then the TMDS_PLL_LOCKED should go high.

Thanks,
Dharani S

Hi Dharani, thank you for your advice. We will check the TMDS clock lines with a scope. However, we think the ADV7610 is enabled and set up correctly and the TMDS clock lines are stable, and then the TMDS_PLL_LOCKED is set to 1. We confirmed 156kHz is output to LRCLK before TMDS_PLL_LOCKED is set, is there a possible cause? The UG-438 has the following description.

Audio DPLL: this clock synthesizer generates the audio clock. As per HDMI specifications, the incoming HDMI clock is divided down by CTS and then multiplied up by N. This audio clock is used as the main clock in the audio stream section. The output of MCLK represents this clock. It takes less than 5msec after a valid ACR packet for this synthesizer to lock.

The clock synthesizer generates the audio clock, but if it takes about 5msec to generate the audio clock through locking on a valid ACR packet, we should assume that the 96kHz clock might be output to the LRCLK until the 48kHz clock is generated. We will check exactly how long 96kHz clock is being output. If this assumption is correct, could you please describe how to define the register configuration to prevent the 96kHz clock output? We would like to know how to control the ADV7610 to prevent unexpected clocks being output to the LRCLK before and after TMDS_PLL_LOCKED is set.

Is there any possible cause for the output of 40.6kHz other than a problem with the clock source or PLL?

Could you please comment on the following two questions?

Q1: The UG states that the output pin drive strength can be controlled by the DR_STR[1:0] bits, but that the ADV7610 does not support tri-statement via dedicated pins. Does this dedicated pin mean the LRCLK and the AP pins? If the LRCLK cannot be set to Hi-Z state, will the clock always be output after POR?

Q2: In order to avoid the phenomenon we confirmed, do we need to take measures that the default setting of FORCE_N_UPDATE should be changed to 1 and forcibly update N and CTS when change is observed?

We have verified our evaluation platform by inputting different audio input sample frequencies like 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, 192 kHz using script and software driver and found the N and CTS values are updated correctly in the HDMI Protocol analyzer which is same as per the HDMI specifications as reference.

Please note that you have to tweak N and CTS values to get good audio out.
Moreover, it is good to use HDMI generator and analyzer for initial development and this would be helpful for debugging the HDMI audio projects

 Are you testing on our eval. board?

 Does the setup work correctly with HDMI input, i.e. are the N and CTS correct?

Thanks,

Dharani S

Hi,

We understood that the ADV7610 does not support Tri-state through dedicated pins, so even if we change the default value of 0x90 register, LRCLK will not be set to Tri-state. Is this correct?

After POR, we will set the FORCE_N_UPDATE bit to 1 and verify the behavior of LRCLK after POR. As a basic operation, is it possible to assume that the LRCLK clock is not output before TDM PLL Locked is set to 1? We would like you to provide a clear answer as to whether there is a difference in the behavior of the LRCLK clock after POR depending on the setting of FORCE_N_UPDATE bit.

Hi,

There are two PLLs in the system, one video PLL that locks the ADC clock to the horizontal input and is set by the PLL_DIV RATIO register.  The other is the audio PLL

The audio PLL will either lock to the TMDS clock or if there is no TMDS clock it will ramp up to max or the limits specified in the spread sheet.   You can free run but limit MCLK to the frequency you need.  It does not need to be locked to the LLC.  I2S and video are 2 separate data streams.

The ADV7610 MCLK is derived from the TMDS clock and CTS/N values in the infoframes.  Also when you are using the analog inputs there will be no MCLK.  I believe you will have to mux in another MCLK which is synchronized the the audio stream you are working with.

ADV7610 simply outputs BCLK and LRCLK of the audio that is received via HDMI. If the received HDMI contains audio with LRCLK = 48KHz, its LRCLK output will be 48KHz. If the received HDMI contains audio with LRCLK = 192KHz, its LRCLK output will be 192KHz.

We suggest customers who are interested in ADV7610 purchase one of our evaluation boards with ADV7611 or ADV7612 to learn the details about receiving and outputting digital video and audio.

Thanks,
Dharani S