The imx8mm integrates adv7280m to process incoming cvbs signals

Hi,

Please note that no of customers been successfully interfaced the ADV7280M with the iMX6 so ensure whether you are using the latest driver software from NXP.

Also note that, until proper termination is achieved, you will not be able to decode Video data from the MIPI CSI-2 signals output by the ADV7280-M.

 As a part of MIPI specification, the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. High speed, Low power mode etc.). The receiver needs to detect the mode of operation and dynamically set its termination accordingly. Note that the Clock signals will only appear correctly when properly terminated.

Note that the Microprocessor / FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the Microprocessor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.

So please ensure your MIPI receiver (Microprocessor/ FPGA) has been configured correctly.

This is described in applications note AN-1337

http://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

For our evaluation of the ADV7280-M we used the MIPI reference termination board which is available from here:

MIPI Test Boards | Interoperability Laboratory

ADI linux drivers can be found at Linux Drivers [Analog Devices Wiki]

ADI do support Linux drivers - they are located here (https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/media/i2c) The ADV728x related content is stored in the ADV7180.c file.

Also, the Linux driver for the ADV7280 branch in the Linux kernel git repository on the ADI github account.

https://github.com/analogdevicesinc/linux/tree/adv7280

Hi, thank you for your reply. The main control I use here is imx8mm lpddr4, not imx6.

According to www.analog.com/.../AN-1337.pdf information here, After careful inspection of the output information mipi data, it is found that the amplitude gap is 440mv in high-speed mode and about 1.2v in low-speed mode. In this case, is there no normal output in mipi data? The problem occurs in the output of adv7280m
 

Here is the configuration I used for reference

What might be the cause here? Which direction should we start the investigation? Could you give some investigation or modification suggestions, thank you

In addition, I have applied for a demo board of adv7280m, but the running software has not been found. The solution I found elsewhere in this forum is to obtain the file through ftp, but I can not get it. I failed to log in to obtain the file. Could you please send the running software of adv7280 demo board directly

With best wishes

Hi, thank you for your reply. The main control I use here is imx8mm lpddr4, not imx6.

According to www.analog.com/.../AN-1337.pdf information here, After careful inspection of the output information mipi data, it is found that the amplitude gap is 440mv in high-speed mode and about 1.2v in low-speed mode. In this case, is there no normal output in mipi data? The problem occurs in the output of adv7280m
 

Here is the configuration I used for reference

What might be the cause here? Which direction should we start the investigation? Could you give some investigation or modification suggestions, thank you

In addition, I have applied for a demo board of adv7280m, but the running software has not been found. The solution I found elsewhere in this forum is to obtain the file through ftp, but I can not get it. I failed to log in to obtain the file. Could you please send the running software of adv7280 demo board directly

With best wishes

Hi,

In interlaced mode the ADV7282-M outputs with a 216 Mbps data rate (MIPI clock frequency 108 MHz).

In progressive mode (i.e. I2P mode on) the ADV7282-M outputs a 432 Mbps data rate (MIPI clock frequency 216 MHz).

The front end of the ADV728x-M converts the analog video signal into an 8-bit ITU656 video stream (8-bit YCrCb 4:2:2).
The 8-bit ITU656 video stream is fed into a MIPI CSI-2 Tx and D-Phy Tx, The MIPI CSI-2 Tx and D-Phy Tx serializes the video stream and outputs the video stream over a MIPI CSI-2 link. See attached diagram.
Note however that the MIPI CIS-2 link remain in the 8-bit YCrCb 4:2:2 color space.
Also note that the MIPI CIS-2 link retains the line and frame timing of the ITU656 specification.
e.g. frame rate output is 50Hz for PAL and 60Hz for NTSC inputs, in interlaced mode odd frames have one extra line than even frames. 

MIPI CSI-2 has two main modes of operation: High Speed and Low Power.

Data Lanes:

High speed mode is used to transmit data. Data is transmitted in a differential manner. A logic high is ~400 mV and a logic low is ~200 mV.
The Low Power mode is entered during horizontal and vertical blanking periods. Low power mode is single ended. A logic high is 1.2 V and a logic low is ~0 V.

Clock Lanes:

Note that after power-up the clock lanes enter high speed mode and will stay in that mode until powered-down. The clock should be 108 MHz in normal mode and 216 MHz in I2P mode.

We also have a software forum at Linux Software Drivers

Did you try with File zila? I used File zila and see the DVP eval program and script files available to download.

What is the problem in your side? Can you try with File zila and provide update?

Please note that when you order EVAL-ADV7282-M eval board, you would receive a piece of paper explaining about how to log in to our FTP site and downloading the register control software for this board.

Also in this pdf, we can find the details of downloading and installing the DVP Eval software 3034.ADV7280installationguideRevA.pdf. 

Please install file zilla from https://filezilla-project.org/FileZilla - The free FTP solution at https://filezilla-project.

Refer this thread for FileZilla settings, https://ez.analog.com/video/f/q-a/6274/eval-adv739xfez

You can refer this FAQ to know about the DVP eval software limitation at DVP Evaluation Software

Also please download the DVP software from here https://ez.analog.com/video/w/documents/658/adv7613-design-support-files

 
Thanks,
Dharani S

Hi, 

The DVP software has been found to run a test, the following is the test results, the demo board as a whole looks like the effect of running on the imx8mm platform.

I have a few questions for you

1. Is this waveform output normal now?

   （If according to introduce here at https://www.analog.com/en/resources/app-notes/an-1337.html That is not the result of the demo board running is also wrong）

2. Is it normal that 0x0c has a value of 0x36?

3. ":Color Bars 576p MIPI Out:" and ": I2P AUTODETECT CVBS Single Ended In Ain 1, 480p/576p MIPI Out:" work the same, is this normal?

Can you give me some more useful clues to check? For example, how to determine whether the output information of mipi is correct and whether some configurations are normally configured? Thank you very much.

The script ran this: I2P AUTODETECT CVBS Single Ended In Ain 1, 480p/576p MIPI Out

This automatically becomes 0x36, right？

The measured CLKN

The measured D0P

Overview Graphics 1.28v "====" -80mv

Bottom graphic: V amplitude 480mv "====" -60mv

Run "Color Bars 576p MIPI Out" image :

With best wishes.

Hi,

1. Please compare your output waveform with MIPI DPHY version 1.00.00 specification and this is the best way whether the output data format is compliance with MIPI-CSI2 Specifications.

Please refer http://www.jmrcubed.com/vr/ref_te/mipi_d_phy_specification_v01-00-00.pdf

And also, these MIPI output waveform details are provided in AN-1337 https://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

Hi,
Using the gst command to capture a video frame to generate an image will hover, press ctrl+c to force the exit, and the size of the generated image will be 0

For this issue, after consulting adi and nxp related forum information, I have a few questions for you :
Q1.ADV7280A-M Can I set a discrete clock mode? How to set it if possible, such as which register or where to set it ?
Q2.([Design Considerations for Connecting Analog Devices Video Decoders to MIPI CSI-2 Mentioned the Receivers] (https://www.analog.com/en/resources/app-notes/an-1337.html) "If the MIPI CSI-2 receiver is initialized after the transmitter device is initialized, the MIPI CSI-2 may never detect the LP to HS mode transition on the clock lane from the transmitter device. If the MIPI CSI-2 receiver does not detect the LP to HS mode transition, it may never start video capture.")  adv7180_s_power is called twice during initialization, the first time the main thing is to set the value 0x00 to 0x00 and the second time the main thing is to set the value 0x00 to 0x00 ,is this process correct
Q3.D-PHY Status,The state of the imx8mm D-PHY receiver has always been ULPS state, which may be the main reason for the failure to capture video frames and generate pictures. May I ask why the receiver has always been in ULPS state? The imx8mm said that the output of ADV7280M was wrong, what should be done here

Thanks,
Best Regards

As per MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2) Version 1.1 states that all CSI-2 transmitters and receivers must support continuous clock behavior on the Clock lane. The continuous clock behavior means that the Clock lane remains in high-speed mode generating active clock signals between the transmissions of data packets. The specification also indicates that transmitters and receivers may optionally support non-continuous clock behavior.

 Please note, the clock lanes are used to clock the output video. After the ADV728x-M is programmed, the clock lanes exit low power mode and remain in high speed mode until the part is reset  or powered down.

 Note: As part of the MIPI specification the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. high speed, low power mode etc). The receiver needs to detect the mode of operation and dynamically set its termination accordingly. Note that the Clock signals will only appear correctly when properly terminated. And also for configuration details refer attached application note.

Please refer this thread have reported same MIPI clock problem  and expert suggested some comments about this issue  https://ez.analog.com/video/f/q-a/6642/adv7280-m-clock-problem/19810#19810

Please make sure with below thing,

      By default the ADV728x-M will output a blue screen when it is in free-run mode. However a number of free-run patterns can be selected instead. See the 'Free Run Operation' section of the ADV728x hardware manual:

https://www.analog.com/media/en/technical-documentation/user-guides/ADV7280_7281_7282_7283_UG-637.pdf

Please note the grabs of the MIPI CSI-2 output packets from the ADV728x-M was captured using a Keysight U4421A Protocol Analyzer.

The MIPI waveforms were captured using a high speed oscilloscope.

Thanks,
Dharani S