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The imx8mm integrates adv7280m to process incoming cvbs signals

Category: Software
Product Number: ADV7280A-M, ADV7280A, ADV7280A

In my scenario, adv7280m is used to process the input cvbs signal on imx8mm, and the data lane is 1. When gst command is used to acquire and process the video stream to generate an image, the size of the generated image is 0. The following is the mipi signal I measured (100m bandwidth, 1g sampling rate oscilloscope).

gst cmd:  

gst-launch-1.0 v4l2src num-buffers=2 device=/dev/video0 ! 'video/x-raw, format=(string)UYVY,

width=720, height=576, interlace-mode=progressive, framerate=25/1' ! jpegenc ! filesink


mipi clkn rate

mipi data(d0P) rate


My question: Does the adv7280m output mipi signal normally, or does the imx8mm receive mipi signal processing problem



  • Hi,

    Please note that no of customers been successfully interfaced the ADV7280M with the iMX6 so ensure whether you are using the latest driver software from NXP.

    Also note that, until proper termination is achieved, you will not be able to decode Video data from the MIPI CSI-2 signals output by the ADV7280-M.

     As a part of MIPI specification, the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. High speed, Low power mode etc.). The receiver needs to detect the mode of operation and dynamically set its termination accordingly. Note that the Clock signals will only appear correctly when properly terminated.

    Note that the Microprocessor / FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the Microprocessor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.

    So please ensure your MIPI receiver (Microprocessor/ FPGA) has been configured correctly.

    This is described in applications note AN-1337

    For our evaluation of the ADV7280-M we used the MIPI reference termination board which is available from here:

    MIPI Test Boards | Interoperability Laboratory

    ADI linux drivers can be found at Linux Drivers [Analog Devices Wiki]

    ADI do support Linux drivers - they are located here ( The ADV728x related content is stored in the ADV7180.c file.

    Also, the Linux driver for the ADV7280 branch in the Linux kernel git repository on the ADI github account.

    Dharani S
  • Hi, thank you for your reply. The main control I use here is imx8mm lpddr4, not imx6.

    According to information here, After careful inspection of the output information mipi data, it is found that the amplitude gap is 440mv in high-speed mode and about 1.2v in low-speed mode. In this case, is there no normal output in mipi data? The problem occurs in the output of adv7280m

    Here is the configuration I used for reference

    What might be the cause here? Which direction should we start the investigation? Could you give some investigation or modification suggestions, thank you

    In addition, I have applied for a demo board of adv7280m, but the running software has not been found. The solution I found elsewhere in this forum is to obtain the file through ftp, but I can not get it. I failed to log in to obtain the file. Could you please send the running software of adv7280 demo board directly

    With best wishes

  • Hi,

    In interlaced mode the ADV7282-M outputs with a 216 Mbps data rate (MIPI clock frequency 108 MHz).

    In progressive mode (i.e. I2P mode on) the ADV7282-M outputs a 432 Mbps data rate (MIPI clock frequency 216 MHz).

    The front end of the ADV728x-M converts the analog video signal into an 8-bit ITU656 video stream (8-bit YCrCb 4:2:2).
    The 8-bit ITU656 video stream is fed into a MIPI CSI-2 Tx and D-Phy Tx, The MIPI CSI-2 Tx and D-Phy Tx serializes the video stream and outputs the video stream over a MIPI CSI-2 link. See attached diagram.
    Note however that the MIPI CIS-2 link remain in the 8-bit YCrCb 4:2:2 color space.
    Also note that the MIPI CIS-2 link retains the line and frame timing of the ITU656 specification.
    frame rate output is 50Hz for PAL and 60Hz for NTSC inputs, in interlaced mode odd frames have one extra line than even frames. 

    MIPI CSI-2 has two main modes of operation: High Speed and Low Power.

    Data Lanes:

    High speed mode is used to transmit data. Data is transmitted in a differential manner. A logic high is ~400 mV and a logic low is ~200 mV.
    The Low Power mode is entered during horizontal and vertical blanking periods. Low power mode is single ended. A logic high is 1.2 V and a logic low is ~0 V.

    Clock Lanes:

    Note that after power-up the clock lanes enter high speed mode and will stay in that mode until powered-down. The clock should be 108 MHz in normal mode and 216 MHz in I2P mode.

    Software drivers for the ADV7280M can be found at

    We also have a software forum at Linux Software Drivers

    Did you try with File zila? I used File zila and see the DVP eval program and script files available to download.

    What is the problem in your side? Can you try with File zila and provide update?

    Please note that when you order EVAL-ADV7282-M eval board, you would receive a piece of paper explaining about how to log in to our FTP site and downloading the register control software for this board.

    Also in this pdf, we can find the details of downloading and installing the DVP Eval software 3034.ADV7280installationguideRevA.pdf

    Please install file zilla from - The free FTP solution at https://filezilla-project.

    Refer this thread for FileZilla settings,

    You can refer this FAQ to know about the DVP eval software limitation at DVP Evaluation Software

    Also please download the DVP software from here

    Dharani S

  • Hi, 

    The DVP software has been found to run a test, the following is the test results, the demo board as a whole looks like the effect of running on the imx8mm platform.

    I have a few questions for you

    1. Is this waveform output normal now?

      (If according to introduce here at That is not the result of the demo board running is also wrong)

    2. Is it normal that 0x0c has a value of 0x36?

    1. ":Color Bars 576p MIPI Out:" and ": I2P AUTODETECT CVBS Single Ended In Ain 1, 480p/576p MIPI Out:" work the same, is this normal?

    Can you give me some more useful clues to check? For example, how to determine whether the output information of mipi is correct and whether some configurations are normally configured? Thank you very much.

    The script ran this: I2P AUTODETECT CVBS Single Ended In Ain 1, 480p/576p MIPI Out

    This automatically becomes 0x36, right?

    The measured CLKN

    The measured D0P

    Overview Graphics 1.28v "====" -80mv

    Bottom graphic: V amplitude 480mv "====" -60mv

    Run "Color Bars 576p MIPI Out" image :

    With best wishes.

  • Hi,

    1. Please compare your output waveform with MIPI DPHY version 1.00.00 specification and this is the best way whether the output data format is compliance with MIPI-CSI2 Specifications.

    Please refer

    And also, these MIPI output waveform details are provided in AN-1337

    2.Yes, it is normal. The default value of Register 0x0C is 0x36, which equates to a value of 0x0D for DEF_Y[5:0]. The default output color is blue.
    3.So, it's normal to have some similarities in terms of resolution and output interface but they are designed for different use cases and functionalities within the ADV7280 chip.
    Configure the VID_SEL bit after setting the INSEL register to get proper video output.
    You can refer this related thread ADV7280A-M MIPI out blue pictrue.
    Dharani S