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CSCM adv7401, results obtained with a CSC configuration cannot be re-visualized using the same configuration.

Category: Hardware
Product Number: ADV7401

The adv7401 chip is being used in the conversion of a non-standard RGB signal using CP. When visualizing the converted image, an execive red gain can be seen, since the red signal has a higher amplitude. By reducing the gain of the red channel and modifying the CSC to balance the tones, a configuration of 1024 for each channel was reached and an appreciable image was presented, but when the card that integrates the adv7401 chip was removed, only a black image was obtained. I would like to know the conciderations when modifying the channel gains and the gains of the CSC matrix. We would also like to know how to improve the synchronization and color gain with respect to the original image.

original                                                                        advadv


  • Hi,

    There is an application note ( describes how to configure the CP to process nonstandard video formats using the following steps:
    1. Choose the appropriate PRIM_MODE/VID_STD.
    2. Program the latch clock.
    3. Program PLL_DIV_RATIO[11:0]
    4. Program FR_LL[10:0]

    Also, refer section 6.4.3 at

    Note: For all non-standard CP PLL modes, the PRIM_MODE and VID_STD must be to set to the nearest available standard to correctly configure the internal parameters of the CP core to decode the specific SD/HD/GR and Interlace/Progressive standard.

    I’ve attached our eval note for the ADV7401 board which includes schematics, layout and bill of materials. You should use this as a reference when working on the ADV7401 layout.ADV7403_EVAL_NOTE_MINI_REVA_aug_07.pdf
    And please let us know, whether you are facing issues particularly with RGB input? Are you able to get free run output without any issues?
    Dharani S
  • Thank you very much for the information, in particular with respect to the rgb input it can be seen with oscilloscope that its voltage levels are almost double the levels of G,B, also mention that it is using HS,VS composite sync. the programming is as follows:

    echo ':RGB 1280x1024 _@ 60 ADV7402 108.000MHz Out through DAC:'
    i2cset -f -y 0 0x21 0x05 0x02 && echo 'Prim_Mode =010b for GR'
    i2cset -f -y 0 0x21 0x06 0x05 && echo 'VID_STD=0101b for 1280x1024 _@ 60'
    i2cset -f -y 0 0x21 0x1D 0x47 && echo 'Enable 28MHz Crystal'
    i2cset -f -y 0 0x21 0x37 0x00 && echo 'Invert PCLK'

    i2cset -f -y 0 0x21 0x3A 0x21 && echo 'latch clock=010b (50Mhz -> 111Mhz), Power Down ADC3'
    i2cset -f -y 0 0x21 0x3B 0x80 && echo 'Enable External Bias'
    i2cset -f -y 0 0x21 0x3C 0x5D && echo 'PLL_QPUMP to 101b'
    i2cset -f -y 0 0x21 0x6A 0x00 && echo 'DLL Phase Adjust'

    i2cset -f -y 0 0x21 0x6B 0xC2 && echo 'sets CPOP_SEL to 0010b 30 Bit Output Pr/Pb pins swapped.'
    i2cset -f -y 0 0x21 0x73 0x10 && echo 'Set auto_gain'
    i2cset -f -y 0 0x21 0x7B 0x11 && echo 'AV CODES disABLEd codes'
    i2cset -f -y 0 0x21 0x85 0x03 && echo 'Enable DS_OUT'
    i2cset -f -y 0 0x21 0x86 0x0B && echo 'Enable stdi_line_count_mode'
    i2cset -f -y 0 0x21 0xF4 0x3F && echo 'Max Drive Strength'

    i2cset -f -y 0 0x21 0x6B 0x80 && echo 'Enable DE output, 24bit R[P9:2]G[P19:12]B[P29:22] output'
    #i2cset -f -y 0 0x21 0x6B 0x82 && echo 'Enable DE output, swap Pr Pb' # <<-- Thinks its Component Input

    #Relating to Sub measurements:
    #HSync pulse width = 1.2us , HSync period width = 20.33us
    i2cset -f -y 0 0x21 0x87 0xE0 && echo '; Man set PLL_DIV_MAN_EN=1 '
    i2cset -f -y 0 0x21 0x87 0xE6 && echo '; Man set PLL_DIV_RATIO 1632=(6)60h'
    i2cset -f -y 0 0x21 0x88 0x60 && echo '; Man set PLL_DIV_RATIO 1632= 6(60)h'
    i2cset -f -y 0 0x21 0x8A 0x90 && echo '; VCO_RANGE_MAN=1'
    i2cset -f -y 0 0x21 0x8A 0xD0 && echo 'VCO Range to 10b'
    i2cset -f -y 0 0x21 0x8F 0x02 && echo 'FR_LL = 583=(2)47h'
    i2cset -f -y 0 0x21 0x90 0x47 && echo 'FR_LL = 583=2(47)h'

    i2cset -f -y 0 0x21 0x0E 0x80 && echo 'ADI Recommended Setting'
    i2cset -f -y 0 0x21 0x52 0x46 && echo 'ADI Recommended Setting'
    i2cset -f -y 0 0x21 0x54 0x00 && echo 'ADI Recommended Setting'
    i2cset -f -y 0 0x21 0x0E 0x00 && echo 'ADI Recommended Setting'

    #Man Gain 12,3,74
    i2cset -f -y 0 0x21 0x73 0xC0      
    i2cset -f -y 0 0x21 0x74 0xC0      
    i2cset -f -y 0 0x21 0x75 0x14      
    i2cset -f -y 0 0x21 0x76 0x4A      

    #OFFSET 0,0,0
    i2cset -f -y 0 0x21 0x77 0x00
    i2cset -f -y 0 0x21 0x78 0x00
    i2cset -f -y 0 0x21 0x79 0x00
    i2cset -f -y 0 0x21 0x7A 0x00
    #CLMP values 1352,894,1640
    i2cset -f -y 0 0x21 0x6C 0xE5
    i2cset -f -y 0 0x21 0x6D 0x48
    i2cset -f -y 0 0x21 0x6E 0x37
    i2cset -f -y 0 0x21 0x6F 0xE6
    i2cset -f -y 0 0x21 0x70 0x68

    #CSC matrix:  [2048 0 0 ; 0 2048 0; 0 0 2048] * 2 + [0 ; 0 ; 150]
    i2cset -f -y 0 0x21 0x52 0x80              
    i2cset -f -y 0 0x21 0x53 0x00              
    i2cset -f -y 0 0x21 0x54 0x00              
    i2cset -f -y 0 0x21 0x55 0x00              
    i2cset -f -y 0 0x21 0x56 0x00              
    i2cset -f -y 0 0x21 0x57 0x04              
    i2cset -f -y 0 0x21 0x58 0x00              
    i2cset -f -y 0 0x21 0x59 0x00              
    i2cset -f -y 0 0x21 0x5A 0x00              
    i2cset -f -y 0 0x21 0x5B 0x00              
    i2cset -f -y 0 0x21 0x5C 0x00              
    i2cset -f -y 0 0x21 0x5D 0x80              
    i2cset -f -y 0 0x21 0x5E 0x00              
    i2cset -f -y 0 0x21 0x5F 0x00              
    i2cset -f -y 0 0x21 0x60 0x00              
    i2cset -f -y 0 0x21 0x61 0x96              
    i2cset -f -y 0 0x21 0x62 0x10              
    i2cset -f -y 0 0x21 0x63 0x00              
    i2cset -f -y 0 0x21 0x64 0x00              
    i2cset -f -y 0 0x21 0x65 0x00              
    i2cset -f -y 0 0x21 0x66 0x00          
  • Hi,

    This seems very strange. Could the issue be with the back end device?

    As per the expert comment, most likely this is because clamping is incorrect, or gain is set incorrectly. This issue can happen sometimes on the nonstandard scripts.

    On a scope – ensure what is the level voltage of blanking level. If blanking voltage level is correct – this means, that decoder clamps correctly, and only offset and gain should be done to the decoder. Below is an example of the offset/gain control.

        42 73  D2 ; Enable Manual Gain and set CH_A gain

       42 74  94 ; Set CH_A and CH_B Gain;

       42 75  A5 ; Set CH_B and CH_C Gain

       42 76  29 ; Set CH_C gain

       42 77  00 ; Set offset to 11d

       42 78  B0 ; Set offset to 11d

       42 79  2C ; Set offset to 11d

       42 7A  0B ; Set offset to 11d

    Improper CSC implementation can also cause a bleeding. Also make sure the offset or gain set wrong or correct.
    Please crosscheck your layout with reference one.

    Also, our expert has created a tool called PCB Trace Impedance Calculator, to calculate trace impedance's on multi-layer PCBs and generate output files for inclusion into layout design documents.

    Also please let us know, whether you have tested this functionality on one of our ADV7401 evaluation boards. And are you able to reproduce the issue using our evaluation board and recommended setting?

    Dharani S