CSCM adv7401, results obtained with a CSC configuration cannot be re-visualized using the same configuration.

Hi,

1. Choose the appropriate PRIM_MODE/VID_STD.
2. Program the latch clock.
3. Program PLL_DIV_RATIO[11:0]
4. Program FR_LL[10:0]

Also, refer section 6.4.3 at 8446.ADV7403_Manuals.zip

Note: For all non-standard CP PLL modes, the PRIM_MODE and VID_STD must be to set to the nearest available standard to correctly configure the internal parameters of the CP core to decode the specific SD/HD/GR and Interlace/Progressive standard.

Thank you very much for the information, in particular with respect to the rgb input it can be seen with oscilloscope that its voltage levels are almost double the levels of G,B, also mention that it is using HS,VS composite sync. the programming is as follows:

echo ':RGB 1280x1024 _@ 60 ADV7402 108.000MHz Out through DAC:'
i2cset -f -y 0 0x21 0x05 0x02 && echo 'Prim_Mode =010b for GR'
i2cset -f -y 0 0x21 0x06 0x05 && echo 'VID_STD=0101b for 1280x1024 _@ 60'
i2cset -f -y 0 0x21 0x1D 0x47 && echo 'Enable 28MHz Crystal'
i2cset -f -y 0 0x21 0x37 0x00 && echo 'Invert PCLK'

i2cset -f -y 0 0x21 0x3A 0x21 && echo 'latch clock=010b (50Mhz -> 111Mhz), Power Down ADC3'
i2cset -f -y 0 0x21 0x3B 0x80 && echo 'Enable External Bias'
i2cset -f -y 0 0x21 0x3C 0x5D && echo 'PLL_QPUMP to 101b'
i2cset -f -y 0 0x21 0x6A 0x00 && echo 'DLL Phase Adjust'

i2cset -f -y 0 0x21 0x6B 0xC2 && echo 'sets CPOP_SEL to 0010b 30 Bit Output Pr/Pb pins swapped.'
i2cset -f -y 0 0x21 0x73 0x10 && echo 'Set auto_gain'
i2cset -f -y 0 0x21 0x7B 0x11 && echo 'AV CODES disABLEd codes'
i2cset -f -y 0 0x21 0x85 0x03 && echo 'Enable DS_OUT'
i2cset -f -y 0 0x21 0x86 0x0B && echo 'Enable stdi_line_count_mode'
i2cset -f -y 0 0x21 0xF4 0x3F && echo 'Max Drive Strength'

i2cset -f -y 0 0x21 0x6B 0x80 && echo 'Enable DE output, 24bit R[P9:2]G[P19:12]B[P29:22] output'
#i2cset -f -y 0 0x21 0x6B 0x82 && echo 'Enable DE output, swap Pr Pb' # <<-- Thinks its Component Input

#Relating to Sub measurements:
#HSync pulse width = 1.2us , HSync period width = 20.33us
i2cset -f -y 0 0x21 0x87 0xE0 && echo '; Man set PLL_DIV_MAN_EN=1 '
i2cset -f -y 0 0x21 0x87 0xE6 && echo '; Man set PLL_DIV_RATIO 1632=(6)60h'
i2cset -f -y 0 0x21 0x88 0x60 && echo '; Man set PLL_DIV_RATIO 1632= 6(60)h'
i2cset -f -y 0 0x21 0x8A 0x90 && echo '; VCO_RANGE_MAN=1'
i2cset -f -y 0 0x21 0x8A 0xD0 && echo 'VCO Range to 10b'
i2cset -f -y 0 0x21 0x8F 0x02 && echo 'FR_LL = 583=(2)47h'
i2cset -f -y 0 0x21 0x90 0x47 && echo 'FR_LL = 583=2(47)h'

i2cset -f -y 0 0x21 0x0E 0x80 && echo 'ADI Recommended Setting'
i2cset -f -y 0 0x21 0x52 0x46 && echo 'ADI Recommended Setting'
i2cset -f -y 0 0x21 0x54 0x00 && echo 'ADI Recommended Setting'
i2cset -f -y 0 0x21 0x0E 0x00 && echo 'ADI Recommended Setting'

Hi,

This seems very strange. Could the issue be with the back end device?

As per the expert comment, most likely this is because clamping is incorrect, or gain is set incorrectly. This issue can happen sometimes on the nonstandard scripts.

On a scope – ensure what is the level voltage of blanking level. If blanking voltage level is correct – this means, that decoder clamps correctly, and only offset and gain should be done to the decoder. Below is an example of the offset/gain control.

    42 73  D2 ; Enable Manual Gain and set CH_A gain

   42 74  94 ; Set CH_A and CH_B Gain;

   42 75  A5 ; Set CH_B and CH_C Gain

   42 76  29 ; Set CH_C gain

   42 77  00 ; Set offset to 11d

   42 78  B0 ; Set offset to 11d

   42 79  2C ; Set offset to 11d

   42 7A  0B ; Set offset to 11d

Also, our expert has created a tool called PCB Trace Impedance Calculator, to calculate trace impedance's on multi-layer PCBs and generate output files for inclusion into layout design documents.

Also please let us know, whether you have tested this functionality on one of our ADV7401 evaluation boards. And are you able to reproduce the issue using our evaluation board and recommended setting?

Thanks,
Dharani S