adv7403 LLC clock

Question

Hi 
 we are uisng adv7403 decoder with kintex fpga , facing issues with LLC clock which is not periodic manner and getting some fluctuations in between making the clock to high for 3 to more cycles when observed in ILA. Configuration is done for PAL camera input

DharaniS · Accepted Answer

Hi, 
 Please note the "NTSC and PAL" follows a different timing. 
 PAL - Total 625-line (50 field per second) - 576 visible lines. 
 NTSC - Total 525-line (60 field per second) - 480 visible lines. 
 Basically, the timing for IN_LOCK and LOST_LOCK will depend on the settings of other controls, such as SRLS, FSCLE, CIL and COL. These status bits can be based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video or on the evaluation of several fields (taking into account the vertical synchronization as well), as defined by SRLS.INST_HLOCK is an instantaneous horizontal lock indicator, so it must be based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video, and is very likely to be faster than the IN_LOCK and LOST_LOCK status bits. 
 Interlaced mode: The even odd field information is included in embedded in the digital synchronization signals. It is also possible to use the VS/FIELD/SFL pin to determine even/odd fields. In interlaced mode, the VS/FIELD/SFL pin is programmed to output field synchronization pulses. 
 Progressive mode: The field bit goes low and stays low in progressive mode. i.e. even/odd information is not sent in embedded digital synchronization signals. The field synchronization pin will go low and stay low in progressive mode. i.e. even/odd information is not over synchronization pins. So even/odd fields no longer exist in progressive mode. 
 
 Thanks, Dharani S)

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adv7403 LLC clock