adv7403 LLC clock

Hi,

Have you tried to create a FPGA load to map the LLC input directly to an output pin and then check that output on a scope to see it has the right frequency?

The LLC is generated from the crystal. Using the ADI proprietary ADLLT algorithm it can vary the LLC frequency by +/-5% to compensate for analog video horizontal lines of video that are too long/short.

Thanks,
Dharani S

hii madam, thank you for your response.

we are not having the availability of evaluation board with us.we followed the evaluation board files. we write the registers as per the evaluation board scripts only. we are giving  PAL input to the decoder and configured the deocder with PAL registers which are  available in  (page no 302 of ) adv7403 manual. but we are facing the LLC clock issue.

Thanks,

sandeep K

Hi,

Based on our expert's suggestion, we are strongly recommending you purchase an evaluation board so that we can rule out any issues with your hardware or software.

Clock stability is very dependent on schematic implementation and layout.  What did you use as a reference design?  We need to make sure that the schematic and layout are as per the reference to see if this is a potential source of the problem.

LLC should have the same levels as VS and HS.  If not, the LLC line going off board has an incorrect load.

Thanks,
Dharani S

Hello mam , I have a doubt about the line numbers in a video output based on the HSYNC signal. If the consecutive positive edges of the HSYNC signal represent the start of new lines, the line numbers would typically be counted sequentially. However, whether they are considered odd or even lines depends on the specific system or convention being used. 

Thanks

sandeep k

Hello mam , I have a doubt about the line numbers in a video output based on the HSYNC signal. If the consecutive positive edges of the HSYNC signal represent the start of new lines, the line numbers would typically be counted sequentially. However, whether they are considered odd or even lines depends on the specific system or convention being used. 

Thanks

sandeep k

Hi,

Please note the "NTSC and PAL" follows a different timing.

PAL -   Total 625-line (50 field per second) - 576 visible lines.

NTSC - Total 525-line (60 field per second) - 480 visible lines.

Basically, the timing for IN_LOCK and LOST_LOCK will depend on the settings of other controls, such as SRLS, FSCLE, CIL and COL. These status bits can be based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video or on the evaluation of several fields (taking into account the vertical synchronization as well), as defined by SRLS.INST_HLOCK is an instantaneous horizontal lock indicator, so it must be based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video, and is very likely to be faster than the IN_LOCK and LOST_LOCK status bits.

Interlaced mode:
     The even odd field information is included in embedded in the digital synchronization signals.
      It is also possible to use the VS/FIELD/SFL pin to determine even/odd fields. In interlaced mode, the VS/FIELD/SFL pin is programmed to output field synchronization pulses.

Progressive mode:
        The field bit goes low and stays low in progressive mode. i.e. even/odd information is not sent in embedded digital synchronization signals.
        The field synchronization pin will go low and stay low in progressive mode. i.e. even/odd information is not over synchronization pins.

So even/odd fields no longer exist in progressive mode.

Thanks,
Dharani S