Category: Datasheet/Specs
Hi,
Customer has confirmed INTRQ1 and INTRQ2.
It was confirmed that INTRQ1 transitions from "H→L→H" in the sequence below.
However, INTRQ2 remains at H.
Are there any other settings required?
| Initial setting | ||||
| Dev_add | Reg_add | Write Val | ||
| Write 0xE0 0x02 FF FF 0x00 | 0xE0 | 0xFF | 0xFF | |
| Read 0xE0 0x01 47 0x01 | 0xE0 | 0x47 | MPU_STIM_INTRQ_MB1 | |
| 00 | ||||
| Read 0xE0 0x01 46 0x01 | 0xE0 | 0x46 | MPU_STIM_INTRQ_MB2 | |
| 00 | ||||
| Read 0xE0 0x01 40 0x01 | 0xE0 | 0x40 | MPU_STIM_INTRQ | |
| 00 | ||||
| Read 0xE0 0x01 41 0x01 | 0xE0 | 0x41 | CP_LOCK_UNLOCK_EDGE_SEL | |
| 20 | ||||
| Read 0xE0 0x01 45 0x01 | 0xE0 | 0x45 | MPU_STIM_INTRQ_CLR | |
| 00 | ||||
| Write 0xE0 0x1D 0x38 | 0xE0 | 0x1D | 0x38 | PDN_INT2 |
| ----------loop--------------- | ||||
| Write 0xE0 0x02 41 24 0x00 | 0xE0 | 0x41 | 0x24 | INT2_EN |
| Write 0xE0 0x02 46 02 0x00 | 0xE0 | 0x46 | 0x02 | MPU_STIM_INTRQ_MB2 |
| Write 0xE0 0x02 47 02 0x00 | 0xE0 | 0x47 | 0x02 | MPU_STIM_INTRQ_MB1 |
| Write 0xE0 0x02 40 04 0x00 | 0xE0 | 0x40 | 0x04 | MPU_STIM_INTRQ |
| Read 0xE0 0x01 43 0x01 | 0xE0 | 0x43 | MPU_STIM_INTRQ_RAW | |
| 42 | ||||
| Read 0xE0 0x01 44 0x01 | 0xE0 | 0x44 | MPU_STIM_INTRQ_ST | |
| 02 | ||||
| Write 0xE0 0x02 40 00 0x00 | 0xE0 | 0x40 | 0x00 | MPU_STIM_INTRQ |
| Write 0xE0 0x02 45 02 0x00 | 0xE0 | 0x45 | 0x02 | MPU_STIM_INTRQ_CLR |
| Read 0xE0 0x01 43 0x01 | 0xE0 | 0x43 | MPU_STIM_INTRQ_RAW | |
| 40 | ||||
| Read 0xE0 0x01 44 0x01 | 0xE0 | 0x44 | MPU_STIM_INTRQ_ST | |
| 00 | ||||
| ----------------------------- |
The register values actually confirmed by the customer are shown below.
| Read E0 1D 0x01 #Setting_confirmation |
| 78 |
| Read E0 3F 0x0C #Setting_confirmation |
| 3F 40 41 42 43 44 45 46 47 48 49 4A : Add 00 00 20 00 40 00 00 00 00 00 00 00 : Data |
| Write E0 1D 38 0x00 #1 |
| Write E0 41 24 0x00 #2 |
| Write E0 46 02 0x00 #3 |
| Write E0 47 02 0x00 #4 |
| Write E0 40 04 0x00 #5 |
| Read E0 3F 0x0C #Setting_confirmation |
| 3F 40 41 42 43 44 45 46 47 48 49 4A : Add 03 04 24 00 42 02 00 02 02 00 00 00 : Data |
| Read E0 43 0x01 #6 |
| 42 |
| Read E0 44 0x01 #6 |
| 02 |
| Read E0 3F 0x0C #Setting_confirmation |
| 3F 40 41 42 43 44 45 46 47 48 49 4A : Add 03 04 24 00 42 02 00 02 02 00 00 00 : Data |
| Write E0 40 00 0x00 #8 |
| Write E0 45 02 0x00 #7 |
| ./tp_i2c /dev/m_i2c1 0xE0 wr 0x01 43 0x01 |
| Read E0 43 0x01 |
| 40 |
| Read E0 44 0x01 |
| 00 |
| Read E0 3F 0x0C #Setting_confirmation |
| 3F 40 41 42 43 44 45 46 47 48 49 4A : Add 00 00 24 00 40 00 00 02 02 00 00 00 : Data |
| Read E0 1D 0x01 #Setting_confirmation |
| 38 |
| Read E0 3F 0x0C #Setting_confirmation |
| 3F 40 41 42 43 44 45 46 47 48 49 4A : Add 00 00 24 00 40 00 00 02 02 00 00 00 : Data |
Best regards.
