ADV7480 I2C NACK error

Hi,

Please ensure whether CEC is enabled or not in ADV7480. If enabled, the bit cec_force_nack (0x27) should be zero. If it is not zero, we will receive NACK message.

Refer the hardware manual: ez.analog.com/.../8816.ADV748x_5F00_Manuals.zip

Generally, to overcome the I2C bus lock / Error, the Slave (i.e Our Video chipset) should follow the sequence as given in our reference script - it is recommended to wait 5ms before you attempt an I2C transaction.

Master Side: I2C bus lock/Error: Please try resetting the I2C master after you do the I2C reset command to the ADV7480. Sometimes the I2C master is having difficulty with the fact that it receives a NACK from the ADV7480 reset write.

So, after implementing the master reset of I2C bus by keeping timeout after providing reset to ADV7480 may solve I2C bus lock/Error.

Thanks,
Dharani S

Hallo Dharani,

Thanks for the reply as highlighted we are only using the recommended script for ADI

":08-10 Free-run MIPI TxA CSI 4-Lane - RGB888, 1280x720p 60Hz:" from the https://www.analog.com/media/en/engineering-tools/design-tools/ADV7481ES3C-VER.3.6c.txt

We dont have any change in the register settings from the above link and still seeing the I2C NACK error. Is this the same recommended setting you are referring to or there is some other?

Regarding CEC, we dont acess CEC (as it is not programmed in the recommended setting). Hence CEC NACK suspect can be ruled out?

Best regards,
Prasad.

Hi,

Please make sure with the below things.

When you do the reset-- it resets quickly so you likely never got the ACK which is probably the I2C Bus Error.
Did you try reading after that to check if registers you had written were back to defaults?
After a reset, it's recommended to wait 5ms before you attempt an I2C transaction. Are you waiting 5ms? Please confirm.

Generally I2C driver performs the following sequence:
Start condition - write operation (Sub address) - Start condition - Read operation (data) - Stop condition
Need to send STOP bit when the whole process reading is done. To terminate a read/write sequence a stop signal must be sent.

If possible, please try to evaluate the same in our evaluation board and let us know about the status.

Thanks,
Dharani S

Hi,

Please make sure with the below things.

When you do the reset-- it resets quickly so you likely never got the ACK which is probably the I2C Bus Error.
Did you try reading after that to check if registers you had written were back to defaults?
After a reset, it's recommended to wait 5ms before you attempt an I2C transaction. Are you waiting 5ms? Please confirm.

Generally I2C driver performs the following sequence:
Start condition - write operation (Sub address) - Start condition - Read operation (data) - Stop condition
Need to send STOP bit when the whole process reading is done. To terminate a read/write sequence a stop signal must be sent.

If possible, please try to evaluate the same in our evaluation board and let us know about the status.

Thanks,
Dharani S

Hi Dharani,

We are not seeing the NACK error for the reset command.  we are seeing it only when we write to

CP Map Address set to 0x44
HDMI RX Map Address set to 0x68
HDMI RX Repeater Map Address set to 0x64

to be precise i have commented the writes which give NACK error. The other writes never return with NACK error.

:08-10 Free-run MIPI TxA CSI 4-Lane - RGB888, 1280x720p 60Hz:

//Init
E0 FF FF ; SW reset
delay 5  ;
E0 01 76 ; ADI Required Write
E0 05 4A ; Setting Vid_Std to 720x480p60
E0 F2 01 ; Enable I2C Read Auto-Increment
E0 F3 4C ; DPLL Map Address Set to 0x4C
E0 F4 44 ; CP Map Address Set to 0x44
E0 F5 68 ; HDMI RX Map Address Set to 0x68
E0 F6 6C ; EDID Map Address Set to 0x6C
E0 F7 64 ; HDMI RX Repeater Map Address Set to 0x64
E0 F8 62 ; HDMI RX Infoframe Map Address Set to 0x62
E0 F9 F0 ; CBUS Map Address Set to 0xF0
E0 FA 82 ; CEC Map Address Set to 0x82
E0 FB F2 ; SDP Main Map Address Set to 0xF2
E0 FC 90 ; CSI-TXB Map Address Set to 0x90
E0 FD 94 ; CSI-TXA Map Address Set to 0x94
E0 00 40 ; Disable chip powerdown & Enable HDMI Rx block
64 40 83 ; Enable HDCP 1.1                              //NACK error
68 00 08 ; Foreground Channel = A                       //NACK error
68 98 FF ; ADI Required Write                           //NACK error
68 99 A3 ; ADI Required Write                           //NACK error
68 9A 00 ; ADI Required Write                           //NACK error
68 9B 0A ; ADI Required Write                           //NACK error
68 9D 40 ; ADI Required Write                           //NACK error
68 CB 09 ; ADI Required Write                           //NACK error
68 3D 10 ; ADI Required Write                           //NACK error
68 3E 7B ; ADI Required Write                           //NACK error
68 3F 5E ; ADI Required Write                           //NACK error
68 4E FE ; ADI Required Write                           //NACK error
68 4F 18 ; ADI Required Write                           //NACK error
68 57 A3 ; ADI Required Write                           //NACK error
68 58 04 ; ADI Required Write                           //NACK error
68 85 10 ; ADI Required Write                           //NACK error
68 83 00 ; Enable All Terminations                      //NACK error
68 A3 01 ; ADI Required Write                            //NACK error
68 BE 00 ; ADI Required Write                            //NACK error
68 6C 01 ; HPA Manual Enable                             //NACK error
68 F8 01 ; HPA Asserted                                       //NACK error
68 0F 00 ; Audio Mute Speed Set to Fastest (Smallest Step Size)       //NACK error
E0 04 02 ; RGB Out of CP
E0 12 F0 ; CSC Depends on ip Packets - SDR 444
E0 17 80 ; Luma & Chroma Values Can Reach 254d
E0 03 86 ; CP-Insert_AV_Code
44 7C 00 ; ADI Required Write                                                             //NACK error
E0 0C E0 ; Enable LLC_DLL & Double LLC Timing
E0 0E DD ; LLC/PIX/SPI PINS TRISTATED AUD Outputs Enabled
E0 10 A0 ; Enable 4-lane CSI Tx & Pixel Port
94 00 84 ; Enable 4-lane MIPI
94 00 A4 ; Set Auto DPHY Timing
94 DB 10 ; ADI Required Write
94 D6 07 ; ADI Required Write
94 C4 0A ; ADI Required Write
94 71 33 ; ADI Required Write
94 72 11 ; ADI Required Write
94 F0 00 ; i2c_dphy_pwdn - 1'b0
94 31 82 ; ADI Required Write
94 1E 40 ; ADI Required Write

Do you have any suggestion why these specific blocks may fail with NACK error? Have you observed I2C NACK errors on eval board?

Best regards,
Prasad.

Also another observation is if we observer I2C NACK error with one of the blocks

CP Map Address set to 0x44
HDMI RX Map Address set to 0x68
HDMI RX Repeater Map Address set to 0x64

We are still able to write to IO MAP and CSI TXA block registers subsequently without error. But if we again write to CP or HDMI RX or HDMI RX repeater block we get NACK error. This means there is no I2C bus error, but the CP, HDMI RX, HDMI RX repeater blocks are somehow not responsive.

Hi,

Please make sure with below things are not happened with other maps, this may cause your part to enter NACK state.   

     1. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, these cause an immediate jump to the idle condition.
     2. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition.
     3. If an invalid subaddress is issued by the user, then the part does not issue an acknowledge and returns to the idle condition.

Configure the I2C writes for the desired power-up configuration. This should be done before configuring any Analog Front End (AFE) features or applying any ADI recommended initialization setting.

Note: Need to send STOP bit when the whole process reading is done. To terminate a read/write sequence a stop signal must be sent. Here you can find the more details about i2c bus specification and timing related details I2C Bus Specification and User Manual

Video components by Analog Devices contain number of I2C map (such as CP Map, IO Map, HDMI Map and other).  Only main maps (such as IO Maps are programmed at start). Therefore, when powering up board and opening CP Map - you may get error. Go first to Main Map (or IO Map) and configure CP Map address to desired registers.

And most importantly, we don't face such spurious issue in our eval board & also till now we didn't receive any complain from customers about this.

So could you please crosscheck the same in our eval board and let us know about it.

Thanks,
Dharani S

Thanks Dharani for the inputs.

We completely understood the 3 points and the note.

Since we are using the script from ADI and we have already disabled the other I2C device on this bus. Is there a possibility of violating the three points you mentioned with the recommended settings?

We currently don't have a eval board hence we are not able to reproduce the issue. Also you already mentioned the issue is not observed by you on eval board.

It is hard for us to understand why only CP,  HDMI RX and HDMI RX Repeater I2C write fail and continue to fail. However IO MAP is still accessible.
Are there any chances these blocks become non responsive?
Is there any IO MAP register with which we can check the status of these blocks?
Do these blocks  ( CP,  HDMI RX and HDMI RX Repeater) have different I2C specification?

Can you elaborate what exactly you mean by

"Configure the I2C writes for the desired power-up configuration."  We follow the Figure 13. Supply Power-Up Sequence, from the data sheet. Is there anything else we need to take care for power up.

Best Regards,
Prasad.

Hi,

Please find the initialization sequence below.
I2C initialization must be carried out in the following order:
1. If required, configure any I2C writes for the desired configuration of the I2C Slave Map addresses.
2. Configure the I2C writes for the desired power-up configuration. (As mentioned in the previous comment)

Please ensure with below things,

1. Make sure the power rails are good
2. Make sure the device is out of reset and the reset goes high after both power rails are stable.
3. Make sure SDA and SCL signals are going to the right pins.
4. Verify the pull up resistors on SDA and SCL
5. Verify the SDA and SCK signals wiggle and are the right amplitude
6. Verify the start command is correct.
7. Check to see if you can access anything else tied to the I2C bus, like eeprom. Tie something to the bus to make sure the bus is working as expected.
8.Please check that the reset and power-down pins are controlled in the manner described in the datasheet "optimal power-up sequence" section.
9. Make sure SDA is really tied to the data line and SCL is really tied to the clock line.
10. Make sure the reset is tied high
11. Please try below sequence,
a. Power up the chip as normal
b. With a jumper wire or probe, pull the reset pin low to get a good solid hardware reset after power up.
c. Try I2C transaction again.
12. Also setting Chip Reset bit is equivalent to controlling the Reset pin on the ADV7401 and will issue a full chip reset.

All I2C registers will be reset to their default values. After the reset sequence, the part will immediately start to acquire the incoming video signal.
The optimal power-up sequence says to:
1. power-up the 3.3V supply,
2. then power-up the 1.8V supply,
3. 5ms wait,
4. then power-up the power down pin,
5. 5ms wait
6. then the reset pin.
7. wait 5ms before I2C communication.

Note: It is recommended to wait 5ms before any further I2C writes are performed.

Thanks,
Dharani S