ADV8005: Can DDR2 signals be routed on the inner layers of the PCB?

I have already checked UG-707 and know that it says that all traces should be kept on the outer layers and the series termination resistors should be placed.

But I want to know the possibilities.

Hi,

Please check our reference designs to know about how we are interfacing the "DDR Signal routing" at Advantiv EVAL-ADV8005-SMZ Video Evaluation Board - Documents - Video - EngineerZone (analog.com).

Thanks,
Dharani S

Hi, Dharani

Thank you for your response.

I've already checked the Evaluation Board layout and now my board's layout is based on it.

My questions are:

- Can DDR signal routing be placed on inner layers?

- If possible, can the series termination registers were removed?

Could you answer these questions please?

Thank you,

hrnrhty

Hi,

- Can DDR signal routing be placed on inner layers?

We believe DDR signal routing can be placed on inner layers.
Inner layers provide additional routing space and allow for more complex and dense circuit layouts.

Please note, traces should be routed on the same side of the PCB as the devices where possible.
If this is not possible, all traces should be kept on the outer layers

- If possible, can the series termination registers were removed?

As per expert comments, you don't absolutely need the series termination resistors if it is a short run but it is recommended to have them.

1) They reduce overshoot and EMI issues. Matches the ADV8005 output impedance to board design impedance.

2) They're a good point to probe to check signal activity.

The input series resistors of the FPGAs do not do the same functionality as source series resistors do.
They just help maintain input termination to the right levels.

Thanks,
Dharani S

Hi, Dharani

Thank you for your help.

Here's what I've understood:

- If the DDR signal routing is short, it can be placed on inner layers

- Series termination registors might not be needed

- However, matching impedance without registers could be challenging

- I also need to consider the probing points in this case

We are planning to measure EMI.

If there are some issues, I'll try to adjust registor impedance first.

If it isn't enough with changing registors, I'll explore moving DDR routing to inner layers using SI simulation.

Thank you,

hrnrhty