AD9398 output clock edges and data edges are not consistent. Data sheet clearly states on p. 10 that the output data should be latched on the rising clock edge, but some data transitions are on falling clock and some on rising clock. Registers set to 4:4:4.
Hi,
Apologies for the delay in providing the response.
Please make sure if you have configured the registers to DDR. DDR Double Data Rate clocks capture data on both the rising and falling edge of the clock.
AD9398 output will be based on the incoming signal. Please let us know what input you are trying to give to AD9398 and also provide your configuration.
Also output rise and fall times of our products depends on the load connected to the pin and impedance of the traces and devices.
Thanks,
Dharani S
Thanks for the response.
The output data is expected to be latched by the following FPGA on the rising edge of each output clock, and the data would therefore transition on the falling clock edge.
Many of the data outputs transition on the falling clock, but other data outputs transition on the rising clock. This data/clock sync is stable for any particular output.
Example output clock and data waveforms:
HDMI RX OUTPUT D7 (DATA CLOCKED OUT ON FALLING CLOCK)
HDMI RX OUTPUT D9 (DATA CLOCKED OUT ON RISING CLOCK)
Register settings:
The clock is 1/2, and the Output Mode bits are "00", which is 4:4:4 mode (normal).
The input clock is 72MHz with the output at 36MHz. The input pixels are duplicated 2x, and the 1/2 clock is intended to output every other input pixel.
Reg 0x25 readback:
$ ir 3 98 25 1
I2C Data 0x32
Outputs are active high, and the clock is not inverted:
Reg 0x24 readback:
$ ir 3 98 24 1
I2C Data 0xFE
Also, at 36MHz output, the rise and fall times and signal integrity are not an issue.
We appreciate comments on what is happening and how to correct it.
Ralph F
