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AD9398 output clock edges and data edges not consistent.

Category: Datasheet/Specs
Product Number: AD9398KSTZ-150

AD9398 output clock edges and data edges are not consistent.  Data sheet clearly states on p. 10 that the output data should be latched on the rising clock edge, but some data transitions are on falling clock and some on rising clock.  Registers set to 4:4:4.

  • Hi,

    Apologies for the delay in providing the response.

    Please make sure if you have configured the registers to DDR. DDR Double Data Rate clocks capture data on both the rising and falling edge of the clock.

    AD9398 output will be based on the incoming signal. Please let us know what input you are trying to give to AD9398 and also provide your configuration.
    Also output rise and fall times of our products depends on the load connected to the pin and impedance of the traces and devices.

    Dharani S

  • Thanks for the response.

    The output data is expected to be latched by the following FPGA on the rising edge of each output clock, and the data would therefore transition on the falling clock edge.

    Many of the data outputs transition on the falling clock, but other data outputs transition on the rising clock.  This data/clock sync is stable for any particular output.

    Example output clock and data waveforms:





    Register settings:

    The clock is 1/2, and the Output Mode bits are "00", which is 4:4:4 mode (normal).

    The input clock is 72MHz with the output at 36MHz.  The input pixels are duplicated 2x, and the 1/2 clock is intended to output every other input pixel.

    Reg 0x25 readback:                                                        

    $ ir 3 98 25 1                                                                 

    I2C Data 0x32

    Outputs are active high, and the clock is not inverted:

    Reg 0x24 readback:

    $ ir 3 98 24 1                                                                 

    I2C Data 0xFE   

    Also, at 36MHz output, the rise and fall times and signal integrity are not an issue.

    We appreciate comments on what is happening and how to correct it.

    Ralph F

  • Hi,

    As per our experts' suggestion, AD9398 is not recommended for new designs and has not been recommended for new designs in quite a while.

    We have been promoting ADV7611 and ADV7612 as an alternative for over 10 years now.

    As a result, our ability to support AD9398 is mostly limited to what is already published on EngineerZone.

    Sorry for the inconvenience.

    Dharani S

  • We understand the LTB status.

    However, this is not for new design. We are experiencing field failures with production products that were originally designed over 10 years ago.  We suspect that the apparently incorrect data and clock sync is resulting in data errors that are intermittent based on timing variations from temperature and part-to-part variation.  Perhaps there were "minor" AD9398 design or fabrication adjustments over the years that made what seems like a flaw become evident.

    It is disappointing that there is no assistance available to help us understand what is happening - especially if it is something in our design that produces this situation.  Otherwise we are left with the conclusion that this ADI product may be defective, which is doubly disturbing.  Anyway, we can provide an AD9398 with these symptoms for testing if ADI is interested.

    Thank you for the initial response,


  • Hi,

    Let me check with AD9398 expert to help you and get back to you soon.


    Dharani S