Trying to get the MAX96717F to generate a 34.375MHz clock for the image sensor

Question

We need MAX96717F to generate a 34.375MHz (=25MHz*110/80 with proper f_vco) clock for the image sensor in ROR mode. 
 According to the MAX96717 datasheet, we have tried programming the DPLL_3 and DPLL_7-10 to: 
 DPLL_3 = 0x92; // config_use_internal_divider_values = 1 
 DPLL_7 = 0x04; // config_div_in = 1, config_div_fb = 110 (L=0) 
 DPLL_8 = 0x37; // config_div_fb = 110 (H=55) 
 DPLL_9 = 0x80; // config_div_out = 80 (L=0x10) 
 DPLL_10 = 0x82; // config_div_out = 80 (H=0x02), config_allow_coarse_change=1 
 But the output clock frequency is about 37.4539MHz (measured using an oscilloscope that measured a 25MHz crystal as 25.0019MHz). 
 How to make the MAX96717F output 110/80 (or 55/40) times the input 25MHz?

DharaniS · Accepted Answer

Hi, 
 Please find our comments below. 
 We are not aware much about this part, hence we have requested to refer the mentioned thread which demonstrated generating 24MHz. We assume that it would be helpful for you to get some support to generate 34.375MHz. 
 For more information, please visit one of the technical support pages on our newly integrated website below for assistance with Maxim Integrated products. 
 EN - www.analog.com/.../technical-support.html CN - support.analog.com/.../ JP - support.analog.com/.../ 
 Thanks, Dharani S)

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Trying to get the MAX96717F to generate a 34.375MHz clock for the image sensor