MAX96717: Reference Clock/DPLL Generation

Question

Hi, I'm trying to interface with GMSL2 solutions[MAX96717F-MAX96724F]. 
 I need MAX96717 to generate 24MHz Clk to the image Sensor. 
 In MAX96717 datasheet, Reference Clock/DPLL Generation, it says that DPLL can be used to generate CLK which in range 1-75MHz. 
 
 Refer to max96717fr-user-guide, I wish to use this scenario. Using 25MHz Xtal / RoR is not be used 
 
 I found no more clue or guide to continue. 
 How Can I generate 24MHz CLK using DPLL?. 
 Which registers should I go to config? or which parameter need? If [fDPLL_OUT = (N.M)/K &times; fREF] is used, where should I found and assigned N M K? 
 
 Thanks, 
 Wipop

AlexShim · Accepted Answer

Hi Wipop Please refer to the below script... //MFP4 Senor clock, 24MHZ 0x84,0x05,0x70,0x0C, // MFP4 RCLK Driving current MAX 0x84,0x03,0xF0,0xD9, // REFGEN_EN: 0b1=enable, REFGEN_PREDEF_FREQ_ALT: 0b1=enable, REFGEN_PREDEF_FREQ:0b01=24MHz(ALT) 0x84,0x00,0x03,0x03, // RCLKSEL: RCLKOUT clock selection, 0b11= Reference PLL(24MHz(ALT)) 0x84,0x00,0x06,0xB0, // RCLKEN: RCLK output, 0b0=disable, 0b1=enable 0x00, 0x64, // delay 
 
 Regards, 
 Alex

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MAX96717: Reference Clock/DPLL Generation

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