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MAX96717: Reference Clock/DPLL Generation

Category: Hardware
Product Number: MAX96717F
Software Version: -

Hi, I'm trying to interface with GMSL2 solutions[MAX96717F-MAX96724F].

I need MAX96717 to generate 24MHz Clk to the image Sensor.

In MAX96717 datasheet, Reference Clock/DPLL Generation, it says that DPLL can be used to generate CLK which in range 1-75MHz.

Refer to max96717fr-user-guide, I wish to use this scenario. Using 25MHz Xtal / RoR is not be used

I found no more clue or guide to continue.

How Can I generate 24MHz CLK using DPLL?. 

Which registers should I go to config? or which parameter need? If [fDPLL_OUT = (N.M)/K × fREF] is used, where should I found and assigned N M K?