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About programming AVD7513

Category: Datasheet/Specs
Product Number: ADV7513


We created a PCB using the ADV7513 and conducted an HDMI certification test, and received the following comments.
Please comment what you think about the error.

1. Video format timing test
The error message is shown below.
--------------------- Frame number = 1 ----------------------
CEA-861E Video format timing error
VSYNC active edge is 144 pixels behind the specified position.
VSYNC inactive edge is 144 pixels behind the specified position.
-------------------------------------------------- -------
The input signal is 861p with CEA-480E video format timing, and we have confirmed that there is no problem with the input timing to the ADV7513.
I looked at the datasheet assuming there was a problem with the polarity of the sync signal.
The description of the 7513x2012 register on page 142 of "ADV0_Programming_Guide revB March 17" is as follows, 
and in case 2 of each Hsync/Vsync, one operation is described for 4 bits. Which operation is that?

0x17[6] Vsync polarity
Case 2: Synchronous adjustment register (0x41[1]) = 0
0 = Sync polarity pass-through 1 = Sync polarity inversion
0 = high polarity

1 = low polarity

0x17[5] Hsync polarity
Case 2: Synchronous adjustment register (0x41[1]) = 0
0 = Sync polarity pass-through 1 = Sync polarity inversion
0 = high polarity

1 = low polarity

2.EDID operation
The error message for the test is shown below.
2 block EDID read: error
None 4 block EDID read: error
Please tell me how to determine the additional block in Figure 0 of "ADV23_Programming_Guide - Revision B-7513 December 2013" and 
the command list when there is an additional block and when there is no additional block. In particular, please tell me the settings for "ParseEDID_DATA", "Additional block required", and "4xC<>Set to desired segment".
The error messages for the interoperability test are shown below.
Even if a DVI sink is connected to the DUT, it will send the HDMI signal with guard bands and data islands instead of the DVI signal.
At what timing should I set HDMI/DVI mode selection (0xAF[1])?
Can I switch HDMI/DVI correctly by writing the current mode of HDMI/DVI or DVI (0xC6[4]) to HDMI/DVI Select (0xAF[1])?
The description of register 0xC6 in the main map says "Default value: 00000000, Register name: Fixed", but does this register (0xC6[4]) store the HDMI/DVI mode?

nice to meet you.


1.ビデオフォーマットのタイミング テストの
--------------------- フレーム番号 = 1 ----------------------
CEA-861E ビデオフォーマットタイミングエラー
「ADV0_Programming_Guide revB March 17」の142ページにある7513x2012レジスタの説明は以下の通りで、各Hsync/Vsyncのケース2では4ビットに対して1つの動作が記述されていますが、それはどの動作ですか?

0x17[6] Vsync極性
ケース2:同期調整レジスタ(0x41[1])= 0
0 = 同期極性パススルー 1 = 同期極性反転
0 = 高極性

1 = 低極性

0x17[5] Hsync極性
ケース2:同期調整レジスタ(0x41[1]) = 0
0 = 同期極性パススルー 1 = 同期極性反転
0 = 高極性

1 = 低極性

「ADV23_Programming_Guide - リビジョンB-7513年2012月」の図0の追加ブロックの判別方法と、追加ブロックがある場合と追加ブロックがない場合のコマンドリストを教えてください。

との相互運用性 テストのエラーメッセージを以下に示します。
HDMI/DVI または DVI の現在のモード (0xC6[4]) を HDMI/DVI Select (0xAF[1]) に書き込むことで、HDMI/DVI を正しく切り替えることができますか?


[edited by: GenevaCooper at 1:30 PM (GMT -4) on 16 Sep 2023]
  • Hi,

       Please find the below comments,

    1. Video format timing test
     Sync related configuration been available in the folder So could you please crosscheck your sync configuration according to your format.
    Kindly note that, '0x72 writes belongs to ADV7513' and let us know about the result.
    2.EDID operation
                Below figure shows how to implement software to read EDID from the receiver using the ADV7513. Please crosscheck from your end and let us know about that.

    Kindly note that, the system can request additional segments only by programming the EDID Segment register (0xC4). An interrupt bit 0x96[2] indicates that a 256-byte EDID read has been completed, and the information is available in the EDID Memory. 

      The system can request only additional segments by programming the EDID Segment register (0xC4).By writing the desired segment number to register 0xC4, the ADV7513 will automatically access the correct portion of the EDID over the DDC lines and load the 256 bytes into the EDID memory. When the action is complete, an EDID ready interrupt will occur to tell the user.

    'DVI & HDMI' mode related configuration also been available here Kindly crosscheck and let us know about it.