Post Go back to editing

ADV7511 - HDMI TX VDMA underflow issue

Category: Software
Product Number: adv7511


my project consist of an application that produces a 3 bytes per pixel RGB image sent to a HDMI monitor. All of this through an FPGA hw design that is made of an DMAController connected to a HDMI_TX, to make it simple.

These ip-core are configured as follow:


Xil_Out32(dmaCAddress + AXI_DMAC_REG_CTRL, 0x0); 								// reset DMAC
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); 				// enable DMAC

	while((Xil_In32(dmaCAddress + AXI_DMAC_REG_TRANSFER_SUBMIT)) != 0x00U)

	Xil_Out32(dmaCAddress + AXI_DMAC_REG_FLAGS, DMA_CYCLIC | DMA_LAST); 				// enable circular mode

	/* DMA size and offset configuration */
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_X_LENGTH, ((hdmiInitParam->hLineActive * BYTES_PER_PIXEL) - 1));	// h size (numero di bytes da trasferire - 1)
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_SRC_STRIDE, (hdmiInitParam->hLineActive * BYTES_PER_PIXEL)); 	// h offset (numero di bytes tra l'inizio di una riga e l'inizio della successiva)
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_Y_LENGTH, (hdmiInitParam->vFrameActive - 1)); 		// v size (numero di righe da trasferire - 1)

 	Xil_Out32(dmaCAddress + AXI_DMAC_REG_SRC_ADDRESS, shMemAddress); 						// start address

interface selected = 24 bit

	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_CTRL), 0x01U); //bypass color sapce conversion.

	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_HTIMING1), ((hdmiInitParam->hLineActive << 16) | hdmiInitParam->hLineWidth));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_HTIMING2), hdmiInitParam->hSyncWidth);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_HTIMING3), ((hdmiInitParam->hEnableMax << 16) | hdmiInitParam->hEnableMin));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_VTIMING1), ((hdmiInitParam->vFrameActive << 16) | hdmiInitParam->vFrameWidth));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_VTIMING2), hdmiInitParam->vSyncWidth);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_VTIMING3), ((hdmiInitParam->vEnableMax << 16) | hdmiInitParam->vEnableMin));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_RESET), 0x1);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_SOURCE_SEL), 0x0);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_SOURCE_SEL), 0x1);

Now, with a 4 bytes per pixel image I have a perfect image on screen. ON THE OTHER HAND if I set the correct number of bytes per pixel (e.g. 3) I have a VDMA UNDERFLOW STATUS read from register 0x0060 of HDMI TX ip-core and, of course, a erroneous image on screen.

Could you please explain me why ? Is there any constraint related to the inner FIFO of HDMI TX ip-core?

thanks in advance,
BR Vincenzo.

  • Hi,

       ADV7511 is basically a parallel to serial converter So what goes in is what comes out.
       When we do video streams compression from 444 to 422 conversions, then the pixel colors are compressed from 8 bytes down to 4 bytes.



  • Hi ,
    thanks for your reply.

    here there is the ADV7511 configuration:

    	LastDetMode[deviceID]							= MODE_INVALID;
    	TransmitterParm[deviceID].Changed				= TRUE;
    	TransmitterParm[deviceID].Mode					= MODE_NONE;
    	TransmitterParm[deviceID].ReqOutputMode			= OUT_MODE_HDMI;
    	TransmitterParm[deviceID].InPixelFormat 		= SDR_444_SEP_SYNC;
    	TransmitterParm[deviceID].InPixelBitsPerColor 	= 8;
    	TransmitterParm[deviceID].InPixelStyle 			= 2;
    	TransmitterParm[deviceID].InPixelAlignment 		= ALIGN_LEFT;
    	TransmitterParm[deviceID].OutPixelEncFormat 	= OUT_ENC_RGB_444;
    	TransmitterParm[deviceID].InColorSpace 			= TX_CS_YCC_601_FULL_RANGE;
    	TransmitterParm[deviceID].OutColorSpace 		= TX_CS_RGB_FULL_RANGE;
    	TransmitterParm[deviceID].AudInterface			= TX_SPDIF;
    	TransmitterParm[deviceID].DebugControl			= 1;
    	MuteState[deviceID]								= MUTE_ENABLE;

    is there anything wrong in your opinion ? I tried changing the InPixelFormat field and the OutPixelFormat field as you suggested (422 instead of 444) but nothing changes.


  • Hi,

      I have stated like, the Pixel color will be compressed from 8 bytes to 4 bytes and according to your statement it seems you are changing the bytes w.r.t pixel image according to your FPGA So could you please post your question on FPGA reference design Since we could see some similar questions posted on this forum and got resolution there.