ADV7511 - HDMI TX VDMA underflow issue

Hello,

my project consist of an application that produces a 3 bytes per pixel RGB image sent to a HDMI monitor. All of this through an FPGA hw design that is made of an DMAController connected to a HDMI_TX, to make it simple.

These ip-core are configured as follow:

DMAC

Xil_Out32(dmaCAddress + AXI_DMAC_REG_CTRL, 0x0); 								// reset DMAC
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); 				// enable DMAC

	while((Xil_In32(dmaCAddress + AXI_DMAC_REG_TRANSFER_SUBMIT)) != 0x00U)
	{
		//Nop
		
	}

	Xil_Out32(dmaCAddress + AXI_DMAC_REG_FLAGS, DMA_CYCLIC | DMA_LAST); 				// enable circular mode

	
	/* DMA size and offset configuration */
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_X_LENGTH, ((hdmiInitParam->hLineActive * BYTES_PER_PIXEL) - 1));	// h size (numero di bytes da trasferire - 1)
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_SRC_STRIDE, (hdmiInitParam->hLineActive * BYTES_PER_PIXEL)); 	// h offset (numero di bytes tra l'inizio di una riga e l'inizio della successiva)
	Xil_Out32(dmaCAddress + AXI_DMAC_REG_Y_LENGTH, (hdmiInitParam->vFrameActive - 1)); 		// v size (numero di righe da trasferire - 1)

 	Xil_Out32(dmaCAddress + AXI_DMAC_REG_SRC_ADDRESS, shMemAddress); 						// start address

HDMI TX
interface selected = 24 bit

	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_CTRL), 0x01U); //bypass color sapce conversion.

	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_HTIMING1), ((hdmiInitParam->hLineActive << 16) | hdmiInitParam->hLineWidth));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_HTIMING2), hdmiInitParam->hSyncWidth);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_HTIMING3), ((hdmiInitParam->hEnableMax << 16) | hdmiInitParam->hEnableMin));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_VTIMING1), ((hdmiInitParam->vFrameActive << 16) | hdmiInitParam->vFrameWidth));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_VTIMING2), hdmiInitParam->vSyncWidth);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_VTIMING3), ((hdmiInitParam->vEnableMax << 16) | hdmiInitParam->vEnableMin));
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_RESET), 0x1);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_SOURCE_SEL), 0x0);
	Xil_Out32((hdmiTxAddress + AXI_HDMI_REG_SOURCE_SEL), 0x1);
	

Now, with a 4 bytes per pixel image I have a perfect image on screen. ON THE OTHER HAND if I set the correct number of bytes per pixel (e.g. 3) I have a VDMA UNDERFLOW STATUS read from register 0x0060 of HDMI TX ip-core and, of course, a erroneous image on screen.

Could you please explain me why ? Is there any constraint related to the inner FIFO of HDMI TX ip-core?

thanks in advance,
BR Vincenzo.