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ADV7619 Recommended for New Designs
The ADV7619 is a high quality, two input, one output (2:1) multiplexed High-Definition Multimedia Interface (HDMI®) receiver. The ADV7619 is offered in...
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ADV7619 on Analog.com

ADV7611 Recommended for New Designs
The ADV7611 is offered in automotive, professional (no HDCP), and industrial versions. The operating temperature range is −40°C to +85°C. The UG-180...
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ADV7611 on Analog.com

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ADV7619 can receive 1080p from HDMI generator (no EDID), but failed to receive 1080p from PC (with EDID)

		
	
				

			

									
					    CharlieT
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Aug 4, 2023 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Software
    
    		        		            		    
    Product Number:  ADV7619 
    
    		        		    		    
    
		    		    
		    			
    
			    
    Hello,
    

    We are using Terasic (HDMI licensee)  HDMI-FMC board and a customized FPGA board to receive 1080p. The system works well with a HDMI video pattern generator (QVS VPG-HL HDMI Video Pattern Generator). All the 1080p data is correctly received. The DE/HS/VS and data are correct (Fig. 1). 
    

    However, when the video source is switched to a laptop's HDMI output, it doesn't work.  The PC can't detect the Terasic board, and the DE/HS/VS and Data don't make sense (the DE pulse changed every 800 pixel data, instead of whole frame; the data is always zero).  (Fig. 2)
    

    We checked many previous posts in this forum. We think the difference (between video pattern generator and PC) is the EDID.  Following the previous post (it is for ADV7611, but we didn't find a similar one for ADV7619 -- so we assume the EDID RAM is the same), we set the EDID internal RAM as well other registers. But we still can't receive valid signals on DE/HS/VS and data lines.  Attached is the register setup for our test. We are stuck on this for a few weeks. Can anyone help ? 
    

    Many thanks.
    

    Charlie 
    

    

    Information 1:
    

     
    

    Fig.1  Valid DE/HS/VS and Data signal with video generator
    

    

    Information 2:
    

     
    

    Fig.2 Invalid DE/HS/VS and Data with PC HDMI output as video source
    

    

    Information 3: previous post on ADV7611 EDID setup:
    

    ez.analog.com/.../how-can-i-use-adv7611-with-an-internal-edid
    

    

    Information 4:  ADV7619 register setup in our test:
    

    ADV7619RegSet(0x98, 0xF4, 0x80); //CEC
     ADV7619RegSet(0x98, 0xF5, 0x7C); //INFOFRAME
     ADV7619RegSet(0x98, 0xF8, 0x4C); //DPLL
     ADV7619RegSet(0x98, 0xF9, 0x64); //KSV
     ADV7619RegSet(0x98, 0xFA, 0x6C); //EDID
     ADV7619RegSet(0x98, 0xFB, 0x68); //HDMI
     ADV7619RegSet(0x98, 0xFD, 0x44); //CP
     //EDID Internal RAM
     ADV7619RegSet(0X64,0X77,0X00); //Disable internal EDID
     ADV7619RegSet(0X6C,0X00,0X00);
     ADV7619RegSet(0X6C,0X01,0XFF);
     ADV7619RegSet(0X6C,0X02,0XFF);
     ADV7619RegSet(0X6C,0X03,0XFF);
     ADV7619RegSet(0X6C,0X04,0XFF);
     ADV7619RegSet(0X6C,0X05,0XFF);
     ADV7619RegSet(0X6C,0X06,0XFF);
     ADV7619RegSet(0X6C,0X07,0X00);
     ADV7619RegSet(0X6C,0X08,0X06);
     ADV7619RegSet(0X6C,0X09,0X8F);
     ADV7619RegSet(0X6C,0X0A,0X07);
     ADV7619RegSet(0X6C,0X0B,0X11);
     ADV7619RegSet(0X6C,0X0C,0X01);
     ADV7619RegSet(0X6C,0X0D,0X00);
     ADV7619RegSet(0X6C,0X0E,0X00);
     ADV7619RegSet(0X6C,0X0F,0X00);
     ADV7619RegSet(0X6C,0X10,0X17);
     ADV7619RegSet(0X6C,0X11,0X11);
     ADV7619RegSet(0X6C,0X12,0X01);
     ADV7619RegSet(0X6C,0X13,0X03);
     ADV7619RegSet(0X6C,0X14,0X80);
     ADV7619RegSet(0X6C,0X15,0X0C);
     ADV7619RegSet(0X6C,0X16,0X09);
     ADV7619RegSet(0X6C,0X17,0X78);
     ADV7619RegSet(0X6C,0X18,0X0A);
     ADV7619RegSet(0X6C,0X19,0X1E);
     ADV7619RegSet(0X6C,0X1A,0XAC);
     ADV7619RegSet(0X6C,0X1B,0X98);
     ADV7619RegSet(0X6C,0X1C,0X59);
     ADV7619RegSet(0X6C,0X1D,0X56);
     ADV7619RegSet(0X6C,0X1E,0X85);
     ADV7619RegSet(0X6C,0X1F,0X28);
     ADV7619RegSet(0X6C,0X20,0X29);
     ADV7619RegSet(0X6C,0X21,0X52);
     ADV7619RegSet(0X6C,0X22,0X57);
     ADV7619RegSet(0X6C,0X23,0X00);
     ADV7619RegSet(0X6C,0X24,0X00);
     ADV7619RegSet(0X6C,0X25,0X00);
     ADV7619RegSet(0X6C,0X26,0X01);
     ADV7619RegSet(0X6C,0X27,0X01);
     ADV7619RegSet(0X6C,0X28,0X01);
     ADV7619RegSet(0X6C,0X29,0X01);
     ADV7619RegSet(0X6C,0X2A,0X01);
     ADV7619RegSet(0X6C,0X2B,0X01);
     ADV7619RegSet(0X6C,0X2C,0X01);
     ADV7619RegSet(0X6C,0X2D,0X01);
     ADV7619RegSet(0X6C,0X2E,0X01);
     ADV7619RegSet(0X6C,0X2F,0X01);
     ADV7619RegSet(0X6C,0X30,0X01);
     ADV7619RegSet(0X6C,0X31,0X01);
     ADV7619RegSet(0X6C,0X32,0X01);
     ADV7619RegSet(0X6C,0X33,0X01);
     ADV7619RegSet(0X6C,0X34,0X01);
     ADV7619RegSet(0X6C,0X35,0X01);
     ADV7619RegSet(0X6C,0X36,0X8C);
     ADV7619RegSet(0X6C,0X37,0X0A);
     ADV7619RegSet(0X6C,0X38,0XD0);
     ADV7619RegSet(0X6C,0X39,0X8A);
     ADV7619RegSet(0X6C,0X3A,0X20);
     ADV7619RegSet(0X6C,0X3B,0XE0);
     ADV7619RegSet(0X6C,0X3C,0X2D);
     ADV7619RegSet(0X6C,0X3D,0X10);
     ADV7619RegSet(0X6C,0X3E,0X10);
     ADV7619RegSet(0X6C,0X3F,0X3E);
     ADV7619RegSet(0X6C,0X40,0X96);
     ADV7619RegSet(0X6C,0X41,0X00);
     ADV7619RegSet(0X6C,0X42,0X81);
     ADV7619RegSet(0X6C,0X43,0X60);
     ADV7619RegSet(0X6C,0X44,0X00);
     ADV7619RegSet(0X6C,0X45,0X00);
     ADV7619RegSet(0X6C,0X46,0X00);
     ADV7619RegSet(0X6C,0X47,0X18);
     ADV7619RegSet(0X6C,0X48,0X01);
     ADV7619RegSet(0X6C,0X49,0X1D);
     ADV7619RegSet(0X6C,0X4A,0X80);
     ADV7619RegSet(0X6C,0X4B,0X18);
     ADV7619RegSet(0X6C,0X4C,0X71);
     ADV7619RegSet(0X6C,0X4D,0X1C);
     ADV7619RegSet(0X6C,0X4E,0X16);
     ADV7619RegSet(0X6C,0X4F,0X20);
     ADV7619RegSet(0X6C,0X50,0X58);
     ADV7619RegSet(0X6C,0X51,0X2C);
     ADV7619RegSet(0X6C,0X52,0X25);
     ADV7619RegSet(0X6C,0X53,0X00);
     ADV7619RegSet(0X6C,0X54,0X81);
     ADV7619RegSet(0X6C,0X55,0X49);
     ADV7619RegSet(0X6C,0X56,0X00);
     ADV7619RegSet(0X6C,0X57,0X00);
     ADV7619RegSet(0X6C,0X58,0X00);
     ADV7619RegSet(0X6C,0X59,0X9E);
     ADV7619RegSet(0X6C,0X5A,0X00);
     ADV7619RegSet(0X6C,0X5B,0X00);
     ADV7619RegSet(0X6C,0X5C,0X00);
     ADV7619RegSet(0X6C,0X5D,0XFC);
     ADV7619RegSet(0X6C,0X5E,0X00);
     ADV7619RegSet(0X6C,0X5F,0X56);
     ADV7619RegSet(0X6C,0X60,0X41);
     ADV7619RegSet(0X6C,0X61,0X2D);
     ADV7619RegSet(0X6C,0X62,0X31);
     ADV7619RegSet(0X6C,0X63,0X38);
     ADV7619RegSet(0X6C,0X64,0X30);
     ADV7619RegSet(0X6C,0X65,0X39);
     ADV7619RegSet(0X6C,0X66,0X41);
     ADV7619RegSet(0X6C,0X67,0X0A);
     ADV7619RegSet(0X6C,0X68,0X20);
     ADV7619RegSet(0X6C,0X69,0X20);
     ADV7619RegSet(0X6C,0X6A,0X20);
     ADV7619RegSet(0X6C,0X6B,0X20);
     ADV7619RegSet(0X6C,0X6C,0X00);
     ADV7619RegSet(0X6C,0X6D,0X00);
     ADV7619RegSet(0X6C,0X6E,0X00);
     ADV7619RegSet(0X6C,0X6F,0XFD);
     ADV7619RegSet(0X6C,0X70,0X00);
     ADV7619RegSet(0X6C,0X71,0X17);
     ADV7619RegSet(0X6C,0X72,0X3D);
     ADV7619RegSet(0X6C,0X73,0X0D);
     ADV7619RegSet(0X6C,0X74,0X2E);
     ADV7619RegSet(0X6C,0X75,0X11);
     ADV7619RegSet(0X6C,0X76,0X00);
     ADV7619RegSet(0X6C,0X77,0X0A);
     ADV7619RegSet(0X6C,0X78,0X20);
     ADV7619RegSet(0X6C,0X79,0X20);
     ADV7619RegSet(0X6C,0X7A,0X20);
     ADV7619RegSet(0X6C,0X7B,0X20);
     ADV7619RegSet(0X6C,0X7C,0X20);
     ADV7619RegSet(0X6C,0X7D,0X20);
     ADV7619RegSet(0X6C,0X7E,0X01);
     ADV7619RegSet(0X6C,0X7F,0X1C);
     ADV7619RegSet(0X6C,0X80,0X02);
     ADV7619RegSet(0X6C,0X81,0X03);
     ADV7619RegSet(0X6C,0X82,0X34);
     ADV7619RegSet(0X6C,0X83,0X71);
     ADV7619RegSet(0X6C,0X84,0X4D);
     ADV7619RegSet(0X6C,0X85,0X82);
     ADV7619RegSet(0X6C,0X86,0X05);
     ADV7619RegSet(0X6C,0X87,0X04);
     ADV7619RegSet(0X6C,0X88,0X01);
     ADV7619RegSet(0X6C,0X89,0X10);
     ADV7619RegSet(0X6C,0X8A,0X11);
     ADV7619RegSet(0X6C,0X8B,0X14);
     ADV7619RegSet(0X6C,0X8C,0X13);
     ADV7619RegSet(0X6C,0X8D,0X1F);
     ADV7619RegSet(0X6C,0X8E,0X06);
     ADV7619RegSet(0X6C,0X8F,0X15);
     ADV7619RegSet(0X6C,0X90,0X03);
     ADV7619RegSet(0X6C,0X91,0X12);
     ADV7619RegSet(0X6C,0X92,0X35);
     ADV7619RegSet(0X6C,0X93,0X0F);
     ADV7619RegSet(0X6C,0X94,0X7F);
     ADV7619RegSet(0X6C,0X95,0X07);
     ADV7619RegSet(0X6C,0X96,0X17);
     ADV7619RegSet(0X6C,0X97,0X1F);
     ADV7619RegSet(0X6C,0X98,0X38);
     ADV7619RegSet(0X6C,0X99,0X1F);
     ADV7619RegSet(0X6C,0X9A,0X07);
     ADV7619RegSet(0X6C,0X9B,0X30);
     ADV7619RegSet(0X6C,0X9C,0X2F);
     ADV7619RegSet(0X6C,0X9D,0X07);
     ADV7619RegSet(0X6C,0X9E,0X72);
     ADV7619RegSet(0X6C,0X9F,0X3F);
     ADV7619RegSet(0X6C,0XA0,0X7F);
     ADV7619RegSet(0X6C,0XA1,0X72);
     ADV7619RegSet(0X6C,0XA2,0X57);
     ADV7619RegSet(0X6C,0XA3,0X7F);
     ADV7619RegSet(0X6C,0XA4,0X00);
     ADV7619RegSet(0X6C,0XA5,0X37);
     ADV7619RegSet(0X6C,0XA6,0X7F);
     ADV7619RegSet(0X6C,0XA7,0X72);
     ADV7619RegSet(0X6C,0XA8,0X83);
     ADV7619RegSet(0X6C,0XA9,0X4F);
     ADV7619RegSet(0X6C,0XAA,0X00);
     ADV7619RegSet(0X6C,0XAB,0X00);
     ADV7619RegSet(0X6C,0XAC,0X67);
     ADV7619RegSet(0X6C,0XAD,0X03);
     ADV7619RegSet(0X6C,0XAE,0X0C);
     ADV7619RegSet(0X6C,0XAF,0X00);
     ADV7619RegSet(0X6C,0XB0,0X10);
     ADV7619RegSet(0X6C,0XB1,0X00);
     ADV7619RegSet(0X6C,0XB2,0X88);
     ADV7619RegSet(0X6C,0XB3,0X2D);
     ADV7619RegSet(0X6C,0XB4,0X00);
     ADV7619RegSet(0X6C,0XB5,0X00);
     ADV7619RegSet(0X6C,0XB6,0X00);
     ADV7619RegSet(0X6C,0XB7,0XFF);
     ADV7619RegSet(0X6C,0XB8,0X00);
     ADV7619RegSet(0X6C,0XB9,0X0A);
     ADV7619RegSet(0X6C,0XBA,0X20);
     ADV7619RegSet(0X6C,0XBB,0X20);
     ADV7619RegSet(0X6C,0XBC,0X20);
     ADV7619RegSet(0X6C,0XBD,0X20);
     ADV7619RegSet(0X6C,0XBE,0X20);
     ADV7619RegSet(0X6C,0XBF,0X20);
     ADV7619RegSet(0X6C,0XC0,0X20);
     ADV7619RegSet(0X6C,0XC1,0X20);
     ADV7619RegSet(0X6C,0XC2,0X20);
     ADV7619RegSet(0X6C,0XC3,0X20);
     ADV7619RegSet(0X6C,0XC4,0X20);
     ADV7619RegSet(0X6C,0XC5,0X20);
     ADV7619RegSet(0X6C,0XC6,0X00);
     ADV7619RegSet(0X6C,0XC7,0X00);
     ADV7619RegSet(0X6C,0XC8,0X00);
     ADV7619RegSet(0X6C,0XC9,0XFF);
     ADV7619RegSet(0X6C,0XCA,0X00);
     ADV7619RegSet(0X6C,0XCB,0X0A);
     ADV7619RegSet(0X6C,0XCC,0X20);
     ADV7619RegSet(0X6C,0XCD,0X20);
     ADV7619RegSet(0X6C,0XCE,0X20);
     ADV7619RegSet(0X6C,0XCF,0X20);
     ADV7619RegSet(0X6C,0XD0,0X20);
     ADV7619RegSet(0X6C,0XD1,0X20);
     ADV7619RegSet(0X6C,0XD2,0X20);
     ADV7619RegSet(0X6C,0XD3,0X20);
     ADV7619RegSet(0X6C,0XD4,0X20);
     ADV7619RegSet(0X6C,0XD5,0X20);
     ADV7619RegSet(0X6C,0XD6,0X20);
     ADV7619RegSet(0X6C,0XD7,0X20);
     ADV7619RegSet(0X6C,0XD8,0X00);
     ADV7619RegSet(0X6C,0XD9,0X00);
     ADV7619RegSet(0X6C,0XDA,0X00);
     ADV7619RegSet(0X6C,0XDB,0XFF);
     ADV7619RegSet(0X6C,0XDC,0X00);
     ADV7619RegSet(0X6C,0XDD,0X0A);
     ADV7619RegSet(0X6C,0XDE,0X20);
     ADV7619RegSet(0X6C,0XDF,0X20);
     ADV7619RegSet(0X6C,0XE0,0X20);
     ADV7619RegSet(0X6C,0XE1,0X20);
     ADV7619RegSet(0X6C,0XE2,0X20);
     ADV7619RegSet(0X6C,0XE3,0X20);
     ADV7619RegSet(0X6C,0XE4,0X20);
     ADV7619RegSet(0X6C,0XE5,0X20);
     ADV7619RegSet(0X6C,0XE6,0X20);
     ADV7619RegSet(0X6C,0XE7,0X20);
     ADV7619RegSet(0X6C,0XE8,0X20);
     ADV7619RegSet(0X6C,0XE9,0X20);
     ADV7619RegSet(0X6C,0XEA,0X00);
     ADV7619RegSet(0X6C,0XEB,0X00);
     ADV7619RegSet(0X6C,0XEC,0X00);
     ADV7619RegSet(0X6C,0XED,0X00);
     ADV7619RegSet(0X6C,0XEE,0X00);
     ADV7619RegSet(0X6C,0XEF,0X00);
     ADV7619RegSet(0X6C,0XF0,0X00);
     ADV7619RegSet(0X6C,0XF1,0X00);
     ADV7619RegSet(0X6C,0XF2,0X00);
     ADV7619RegSet(0X6C,0XF3,0X00);
     ADV7619RegSet(0X6C,0XF4,0X00);
     ADV7619RegSet(0X6C,0XF5,0X00);
     ADV7619RegSet(0X6C,0XF6,0X00);
     ADV7619RegSet(0X6C,0XF7,0X00);
     ADV7619RegSet(0X6C,0XF8,0X00);
     ADV7619RegSet(0X6C,0XF9,0X00);
     ADV7619RegSet(0X6C,0XFA,0X00);
     ADV7619RegSet(0X6C,0XFB,0X00);
     ADV7619RegSet(0X6C,0XFC,0X00);
     ADV7619RegSet(0X6C,0XFD,0X00);
     ADV7619RegSet(0X6C,0XFE,0X00);
     ADV7619RegSet(0X6C,0XFF,0XDA);
     ADV7619RegSet(0X64,0X77,0X00); //Set the Most Significant Bit of the SPA location to 0
     ADV7619RegSet(0X64,0X52,0X20); //Set the SPA for port B.
     ADV7619RegSet(0X64,0X53,0X00); //Set the SPA for port B.
     ADV7619RegSet(0X64,0X70,0X9E); //Set the Least Significant Byte of the SPA location
     ADV7619RegSet(0X64,0X74,0X03); //Enable the Internal EDID for Ports
    

    ADV7619RegSet(0x68, 0xC0, 0x03); //ADI Required Write
     ADV7619RegSet(0x98, 0x01, 0x06); //Prim_Mode =110b HDMI-GR
     ADV7619RegSet(0x98, 0x02, 0xF7); //Auto CSC, 0xRGB, 0xSet op_656 bit
     ADV7619RegSet(0x98, 0x03, 0x82); //24 bit SDR 422 Mode 0
     ADV7619RegSet(0x98, 0x05, 0x28); //AV Codes Off
     ADV7619RegSet(0x98, 0x06, 0xA0); //No inversion on VS,HS pins
     ADV7619RegSet(0x98, 0x0C, 0x42); //Power up part
     ADV7619RegSet(0x98, 0x15, 0x80); //Disable Tristate of Pins
     ADV7619RegSet(0x98, 0x19, 0x83); //LLC DLL phase
     ADV7619RegSet(0x98, 0x33, 0x40); //LLC DLL MUX enable
     ADV7619RegSet(0x44, 0xBA, 0x01); //Set HDMI FreeRun
     ADV7619RegSet(0x44, 0x6C, 0x00); //Required ADI write
     ADV7619RegSet(0x64, 0x40, 0x81); //Disable HDCP 1.1 features
     ADV7619RegSet(0x4C, 0xB5, 0x01); //Setting MCLK to 256Fs
     ADV7619RegSet(0x68, 0xC0, 0x03); //ADI Required write
     ADV7619RegSet(0x68, 0x00, 0x08); //Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)
     ADV7619RegSet(0x68, 0x02, 0x03); //ALL BG Ports enabled
     ADV7619RegSet(0x68, 0x03, 0x98); //ADI Required Write
     ADV7619RegSet(0x68, 0x10, 0xA5); //ADI Required Write
     ADV7619RegSet(0x68, 0x1B, 0x08); //ADI Required Write
     ADV7619RegSet(0x68, 0x45, 0x04); //ADI Required Write
     ADV7619RegSet(0x68, 0x97, 0xC0); //ADI Required Write
     ADV7619RegSet(0x68, 0x3D, 0x10); //ADI Required Write
     ADV7619RegSet(0x68, 0x3E, 0x69); //ADI Required Write
     ADV7619RegSet(0x68, 0x3F, 0x46); //ADI Required Write
     ADV7619RegSet(0x68, 0x4E, 0xFE); //ADI Required Write
     ADV7619RegSet(0x68, 0x4F, 0x08); //ADI Required Write
     ADV7619RegSet(0x68, 0x50, 0x00); //ADI Required Write
     ADV7619RegSet(0x68, 0x57, 0xA3); //ADI Required Write
     ADV7619RegSet(0x68, 0x58, 0x07); //ADI Required Write
     ADV7619RegSet(0x68, 0x6F, 0x08); //ADI Required Write
     ADV7619RegSet(0x68, 0x83, 0xFC); //Enable clock terminators for port A & B
     ADV7619RegSet(0x68, 0x84, 0x03); //ADI Required Write
     ADV7619RegSet(0x68, 0x85, 0x11); //ADI Required Write
     ADV7619RegSet(0x68, 0x86, 0x9B); //ADI Required Write
     ADV7619RegSet(0x68, 0x89, 0x03); //ADI Required Write
     ADV7619RegSet(0x68, 0x9B, 0x03); //ADI Required Write
     ADV7619RegSet(0x68, 0x93, 0x03); //ADI Required Write
     ADV7619RegSet(0x68, 0x5A, 0x80); //ADI Required Write
     ADV7619RegSet(0x68, 0x9C, 0x80); //ADI Required Write
     ADV7619RegSet(0x68, 0x9C, 0xC0); //ADI Required Write
     ADV7619RegSet(0x68, 0x9C, 0x00); //ADI Required Write
     ADV7619RegSet(0x72, 0x01, 0x00); //Set N Value(6144)
     ADV7619RegSet(0x72, 0x02, 0x18); //Set N Value(6144)
     ADV7619RegSet(0x72, 0x03, 0x00); //Set N Value(6144)
     ADV7619RegSet(0x72, 0x15, 0x01); //24bit Input 422 (YCrCb) with Separate Syncs, 0x44.1kHz fs
     ADV7619RegSet(0x72, 0x16, 0x61); //YCrCb 444
     ADV7619RegSet(0x72, 0x18, 0x46); //CSC disabled
     ADV7619RegSet(0x72, 0x3B, 0x80); //PR Auto Mode
     ADV7619RegSet(0x72, 0x40, 0x80); //General Control Packet Enable
     ADV7619RegSet(0x72, 0x41, 0x10); //Power Down control
     ADV7619RegSet(0x72, 0x48, 0x08); //Data right justified
     ADV7619RegSet(0x72, 0x49, 0xA8); //Set Dither_mode - 12-to-10 bit
     ADV7619RegSet(0x72, 0x4C, 0x04); //8 bit Output
     ADV7619RegSet(0x72, 0x55, 0x00); //Set RGB 444 in AVinfo Frame
     ADV7619RegSet(0x72, 0x56, 0x08); //Set active format Aspect
     ADV7619RegSet(0x72, 0x96, 0x20); //HPD Interrupt clear
     ADV7619RegSet(0x72, 0x98, 0x03); //ADI Required Write
     ADV7619RegSet(0x72, 0x99, 0x02); //ADI Required Write
     ADV7619RegSet(0x72, 0x9C, 0x30); //PLL Filter R1 Value
     ADV7619RegSet(0x72, 0x9D, 0x61); //Set clock divide
     ADV7619RegSet(0x72, 0xA2, 0xA4); //ADI Required Write
     ADV7619RegSet(0x72, 0xA3, 0xA4); //ADI Required Write
     ADV7619RegSet(0x72, 0xAF, 0x16); //Set HDMI Mode
     ADV7619RegSet(0x72, 0xBA, 0x60); //No clock delay
     ADV7619RegSet(0x72, 0xDE, 0x9C); //ADI Required Write
     ADV7619RegSet(0x72, 0xE4, 0x60); //VCO Swing Reference Voltage
     ADV7619RegSet(0x72, 0xFA, 0x7D); //Nbr of times to search for good phase
    

    /* Enable EDID for PC HDMI output */
     ADV7619RegSet(0x64, 0x74, 0x3); //EDID_A_ENABLE, Addr 64 (Repeater), Address 0x74[0](port A) Address 0x74[1] (portB)
    
			
    
			
									
		                             
                        

    
    
                                            
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      •  Analog Employees  
      •  Super User  
      
            
						
                            
            
            				
            
                on Aug 7, 2023 7:02 AM
            
            
						
			            		
      
		
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      Hi,
      

        YES, PC generally do not work unless they see a valid EDID & PC will only recognize a sink only when they detect an valid EDID .
      

      Sometimes PC has failed to get the correct EDID, so toggle the HPA line to force the PC to re-read the EDID (Follow below sequence) and then check whether you could able to read the 256 bytes.
      1) ADV7619 HDMI 0x68 0x6C[0] = 1, HPA_MAN_VALUE_X
      2) ADV7619 IO 0x98 0x20[3] = 0, HPA_A pin active
      3) ADV7619 IO 0x98 0x20[7] = 0, HPA_MAN_VALUE_A, sets HPA low
      4) load up the EDID
      5) ADV7619 IO 0x98 0x20[7] = 1, HPA_MAN_VALUE_A, sets HPS high, forces source to reload EDID.
      

      Also please ensure with below when bringing up the board & make sure with following sequence.
       1) Disconnect PC from 7619
       2) Run your script
       3) Configure EDID
       4) Configure SPA registers
       5) Plug PC into 7619. this should cause the PC to read the EDID.
      

      When comparing the configuration with reference script ":02-07 720p,1080i,1080p In - 24-bit YCbCr 422 Out: " and we observed below changes with shared configuration. Kindly crosscheck at your end.
      

       
      

      

      Thanks,
      

      Poornima
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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                on Aug 29, 2023 7:53 AM
            
            
												
						in reply to PoornimaSubramani
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hello Poornima,  
        

        Thank you for the instructions.  In the last two weeks, we tried different edit setup, but still can't get it work.  We failed to see any of PCs detect adv7619 when it is connected with the HDMI. Can you help ?   
        

        I attached our code for edid setup, can you help to check if anything wrong ?   Since I can only find the edid data for adv7611, I assume the adv7619 is using the similar edid data.  I have the following questions about your response. 
        

        1. What is the difference between step 2), 3) and 4).  For us, the only main code is to setup edid so adv7619 can talk with a PC.  We used the attached code to run this task. 
        

        2. What is the SPA registers ?  Do you refer to HPA reset register ? 
        

        3. What do you refer "whether you could able to read the 256 bytes" ?  Do you mean read from adv7619 via I2C (which we used to write) ?  Or do you mean the PC somehow can read these 256 bytes ? 
        

        Many thanks for your kind help.
        

        Charlie
        

        

        --------------------------- setup code for adv7619 edid ----------------
        

        int edid ()
        {
         writeADV7619Reg(0x98, 0xF4, 0x80); //CEC
         writeADV7619Reg(0x98, 0xF5, 0x7C); //INFOFRAME
         writeADV7619Reg(0x98, 0xF8, 0x4C); //DPLL
         writeADV7619Reg(0x98, 0xF9, 0x64); //KSV
         writeADV7619Reg(0x98, 0xFA, 0x6C); //EDID
         writeADV7619Reg(0x98, 0xFB, 0x68); //HDMI
         writeADV7619Reg(0x98, 0xFD, 0x44); //CP
        

        //EDID RAM
         writeADV7619Reg(0X64,0X77,0X00); //Disable internal EDID
         writeADV7619Reg(0X6C,0X00,0X00);
         writeADV7619Reg(0X6C,0X01,0XFF);
         writeADV7619Reg(0X6C,0X02,0XFF);
         writeADV7619Reg(0X6C,0X03,0XFF);
         writeADV7619Reg(0X6C,0X04,0XFF);
         writeADV7619Reg(0X6C,0X05,0XFF);
         writeADV7619Reg(0X6C,0X06,0XFF);
         writeADV7619Reg(0X6C,0X07,0X00);
         writeADV7619Reg(0X6C,0X08,0X06);
         writeADV7619Reg(0X6C,0X09,0X8F);
         writeADV7619Reg(0X6C,0X0A,0X07);
         writeADV7619Reg(0X6C,0X0B,0X11);
         writeADV7619Reg(0X6C,0X0C,0X01);
         writeADV7619Reg(0X6C,0X0D,0X00);
         writeADV7619Reg(0X6C,0X0E,0X00);
         writeADV7619Reg(0X6C,0X0F,0X00);
         writeADV7619Reg(0X6C,0X10,0X17);
         writeADV7619Reg(0X6C,0X11,0X11);
         writeADV7619Reg(0X6C,0X12,0X01);
         writeADV7619Reg(0X6C,0X13,0X03);
         writeADV7619Reg(0X6C,0X14,0X80);
         writeADV7619Reg(0X6C,0X15,0X0C);
         writeADV7619Reg(0X6C,0X16,0X09);
         writeADV7619Reg(0X6C,0X17,0X78);
         writeADV7619Reg(0X6C,0X18,0X0A);
         writeADV7619Reg(0X6C,0X19,0X1E);
         writeADV7619Reg(0X6C,0X1A,0XAC);
         writeADV7619Reg(0X6C,0X1B,0X98);
         writeADV7619Reg(0X6C,0X1C,0X59);
         writeADV7619Reg(0X6C,0X1D,0X56);
         writeADV7619Reg(0X6C,0X1E,0X85);
         writeADV7619Reg(0X6C,0X1F,0X28);
         writeADV7619Reg(0X6C,0X20,0X29);
         writeADV7619Reg(0X6C,0X21,0X52);
         writeADV7619Reg(0X6C,0X22,0X57);
         writeADV7619Reg(0X6C,0X23,0X00);
         writeADV7619Reg(0X6C,0X24,0X00);
         writeADV7619Reg(0X6C,0X25,0X00);
         writeADV7619Reg(0X6C,0X26,0X01);
         writeADV7619Reg(0X6C,0X27,0X01);
         writeADV7619Reg(0X6C,0X28,0X01);
         writeADV7619Reg(0X6C,0X29,0X01);
         writeADV7619Reg(0X6C,0X2A,0X01);
         writeADV7619Reg(0X6C,0X2B,0X01);
         writeADV7619Reg(0X6C,0X2C,0X01);
         writeADV7619Reg(0X6C,0X2D,0X01);
         writeADV7619Reg(0X6C,0X2E,0X01);
         writeADV7619Reg(0X6C,0X2F,0X01);
         writeADV7619Reg(0X6C,0X30,0X01);
         writeADV7619Reg(0X6C,0X31,0X01);
         writeADV7619Reg(0X6C,0X32,0X01);
         writeADV7619Reg(0X6C,0X33,0X01);
         writeADV7619Reg(0X6C,0X34,0X01);
         writeADV7619Reg(0X6C,0X35,0X01);
         writeADV7619Reg(0X6C,0X36,0X8C);
         writeADV7619Reg(0X6C,0X37,0X0A);
         writeADV7619Reg(0X6C,0X38,0XD0);
         writeADV7619Reg(0X6C,0X39,0X8A);
         writeADV7619Reg(0X6C,0X3A,0X20);
         writeADV7619Reg(0X6C,0X3B,0XE0);
         writeADV7619Reg(0X6C,0X3C,0X2D);
         writeADV7619Reg(0X6C,0X3D,0X10);
         writeADV7619Reg(0X6C,0X3E,0X10);
         writeADV7619Reg(0X6C,0X3F,0X3E);
         writeADV7619Reg(0X6C,0X40,0X96);
         writeADV7619Reg(0X6C,0X41,0X00);
         writeADV7619Reg(0X6C,0X42,0X81);
         writeADV7619Reg(0X6C,0X43,0X60);
         writeADV7619Reg(0X6C,0X44,0X00);
         writeADV7619Reg(0X6C,0X45,0X00);
         writeADV7619Reg(0X6C,0X46,0X00);
         writeADV7619Reg(0X6C,0X47,0X18);
         writeADV7619Reg(0X6C,0X48,0X01);
         writeADV7619Reg(0X6C,0X49,0X1D);
         writeADV7619Reg(0X6C,0X4A,0X80);
         writeADV7619Reg(0X6C,0X4B,0X18);
         writeADV7619Reg(0X6C,0X4C,0X71);
         writeADV7619Reg(0X6C,0X4D,0X1C);
         writeADV7619Reg(0X6C,0X4E,0X16);
         writeADV7619Reg(0X6C,0X4F,0X20);
         writeADV7619Reg(0X6C,0X50,0X58);
         writeADV7619Reg(0X6C,0X51,0X2C);
         writeADV7619Reg(0X6C,0X52,0X25);
         writeADV7619Reg(0X6C,0X53,0X00);
         writeADV7619Reg(0X6C,0X54,0X81);
         writeADV7619Reg(0X6C,0X55,0X49);
         writeADV7619Reg(0X6C,0X56,0X00);
         writeADV7619Reg(0X6C,0X57,0X00);
         writeADV7619Reg(0X6C,0X58,0X00);
         writeADV7619Reg(0X6C,0X59,0X9E);
         writeADV7619Reg(0X6C,0X5A,0X00);
         writeADV7619Reg(0X6C,0X5B,0X00);
         writeADV7619Reg(0X6C,0X5C,0X00);
         writeADV7619Reg(0X6C,0X5D,0XFC);
         writeADV7619Reg(0X6C,0X5E,0X00);
         writeADV7619Reg(0X6C,0X5F,0X56);
         writeADV7619Reg(0X6C,0X60,0X41);
         writeADV7619Reg(0X6C,0X61,0X2D);
         writeADV7619Reg(0X6C,0X62,0X31);
         writeADV7619Reg(0X6C,0X63,0X38);
         writeADV7619Reg(0X6C,0X64,0X30);
         writeADV7619Reg(0X6C,0X65,0X39);
         writeADV7619Reg(0X6C,0X66,0X41);
         writeADV7619Reg(0X6C,0X67,0X0A);
         writeADV7619Reg(0X6C,0X68,0X20);
         writeADV7619Reg(0X6C,0X69,0X20);
         writeADV7619Reg(0X6C,0X6A,0X20);
         writeADV7619Reg(0X6C,0X6B,0X20);
         writeADV7619Reg(0X6C,0X6C,0X00);
         writeADV7619Reg(0X6C,0X6D,0X00);
         writeADV7619Reg(0X6C,0X6E,0X00);
         writeADV7619Reg(0X6C,0X6F,0XFD);
         writeADV7619Reg(0X6C,0X70,0X00);
         writeADV7619Reg(0X6C,0X71,0X17);
         writeADV7619Reg(0X6C,0X72,0X3D);
         writeADV7619Reg(0X6C,0X73,0X0D);
         writeADV7619Reg(0X6C,0X74,0X2E);
         writeADV7619Reg(0X6C,0X75,0X11);
         writeADV7619Reg(0X6C,0X76,0X00);
         writeADV7619Reg(0X6C,0X77,0X0A);
         writeADV7619Reg(0X6C,0X78,0X20);
         writeADV7619Reg(0X6C,0X79,0X20);
         writeADV7619Reg(0X6C,0X7A,0X20);
         writeADV7619Reg(0X6C,0X7B,0X20);
         writeADV7619Reg(0X6C,0X7C,0X20);
         writeADV7619Reg(0X6C,0X7D,0X20);
         writeADV7619Reg(0X6C,0X7E,0X01);
         writeADV7619Reg(0X6C,0X7F,0X1C);
         writeADV7619Reg(0X6C,0X80,0X02);
         writeADV7619Reg(0X6C,0X81,0X03);
         writeADV7619Reg(0X6C,0X82,0X34);
         writeADV7619Reg(0X6C,0X83,0X71);
         writeADV7619Reg(0X6C,0X84,0X4D);
         writeADV7619Reg(0X6C,0X85,0X82);
         writeADV7619Reg(0X6C,0X86,0X05);
         writeADV7619Reg(0X6C,0X87,0X04);
         writeADV7619Reg(0X6C,0X88,0X01);
         writeADV7619Reg(0X6C,0X89,0X10);
         writeADV7619Reg(0X6C,0X8A,0X11);
         writeADV7619Reg(0X6C,0X8B,0X14);
         writeADV7619Reg(0X6C,0X8C,0X13);
         writeADV7619Reg(0X6C,0X8D,0X1F);
         writeADV7619Reg(0X6C,0X8E,0X06);
         writeADV7619Reg(0X6C,0X8F,0X15);
         writeADV7619Reg(0X6C,0X90,0X03);
         writeADV7619Reg(0X6C,0X91,0X12);
         writeADV7619Reg(0X6C,0X92,0X35);
         writeADV7619Reg(0X6C,0X93,0X0F);
         writeADV7619Reg(0X6C,0X94,0X7F);
         writeADV7619Reg(0X6C,0X95,0X07);
         writeADV7619Reg(0X6C,0X96,0X17);
         writeADV7619Reg(0X6C,0X97,0X1F);
         writeADV7619Reg(0X6C,0X98,0X38);
         writeADV7619Reg(0X6C,0X99,0X1F);
         writeADV7619Reg(0X6C,0X9A,0X07);
         writeADV7619Reg(0X6C,0X9B,0X30);
         writeADV7619Reg(0X6C,0X9C,0X2F);
         writeADV7619Reg(0X6C,0X9D,0X07);
         writeADV7619Reg(0X6C,0X9E,0X72);
         writeADV7619Reg(0X6C,0X9F,0X3F);
         writeADV7619Reg(0X6C,0XA0,0X7F);
         writeADV7619Reg(0X6C,0XA1,0X72);
         writeADV7619Reg(0X6C,0XA2,0X57);
         writeADV7619Reg(0X6C,0XA3,0X7F);
         writeADV7619Reg(0X6C,0XA4,0X00);
         writeADV7619Reg(0X6C,0XA5,0X37);
         writeADV7619Reg(0X6C,0XA6,0X7F);
         writeADV7619Reg(0X6C,0XA7,0X72);
         writeADV7619Reg(0X6C,0XA8,0X83);
         writeADV7619Reg(0X6C,0XA9,0X4F);
         writeADV7619Reg(0X6C,0XAA,0X00);
         writeADV7619Reg(0X6C,0XAB,0X00);
         writeADV7619Reg(0X6C,0XAC,0X67);
         writeADV7619Reg(0X6C,0XAD,0X03);
         writeADV7619Reg(0X6C,0XAE,0X0C);
         writeADV7619Reg(0X6C,0XAF,0X00);
         writeADV7619Reg(0X6C,0XB0,0X10);
         writeADV7619Reg(0X6C,0XB1,0X00);
         writeADV7619Reg(0X6C,0XB2,0X88);
         writeADV7619Reg(0X6C,0XB3,0X2D);
         writeADV7619Reg(0X6C,0XB4,0X00);
         writeADV7619Reg(0X6C,0XB5,0X00);
         writeADV7619Reg(0X6C,0XB6,0X00);
         writeADV7619Reg(0X6C,0XB7,0XFF);
         writeADV7619Reg(0X6C,0XB8,0X00);
         writeADV7619Reg(0X6C,0XB9,0X0A);
         writeADV7619Reg(0X6C,0XBA,0X20);
         writeADV7619Reg(0X6C,0XBB,0X20);
         writeADV7619Reg(0X6C,0XBC,0X20);
         writeADV7619Reg(0X6C,0XBD,0X20);
         writeADV7619Reg(0X6C,0XBE,0X20);
         writeADV7619Reg(0X6C,0XBF,0X20);
         writeADV7619Reg(0X6C,0XC0,0X20);
         writeADV7619Reg(0X6C,0XC1,0X20);
         writeADV7619Reg(0X6C,0XC2,0X20);
         writeADV7619Reg(0X6C,0XC3,0X20);
         writeADV7619Reg(0X6C,0XC4,0X20);
         writeADV7619Reg(0X6C,0XC5,0X20);
         writeADV7619Reg(0X6C,0XC6,0X00);
         writeADV7619Reg(0X6C,0XC7,0X00);
         writeADV7619Reg(0X6C,0XC8,0X00);
         writeADV7619Reg(0X6C,0XC9,0XFF);
         writeADV7619Reg(0X6C,0XCA,0X00);
         writeADV7619Reg(0X6C,0XCB,0X0A);
         writeADV7619Reg(0X6C,0XCC,0X20);
         writeADV7619Reg(0X6C,0XCD,0X20);
         writeADV7619Reg(0X6C,0XCE,0X20);
         writeADV7619Reg(0X6C,0XCF,0X20);
         writeADV7619Reg(0X6C,0XD0,0X20);
         writeADV7619Reg(0X6C,0XD1,0X20);
         writeADV7619Reg(0X6C,0XD2,0X20);
         writeADV7619Reg(0X6C,0XD3,0X20);
         writeADV7619Reg(0X6C,0XD4,0X20);
         writeADV7619Reg(0X6C,0XD5,0X20);
         writeADV7619Reg(0X6C,0XD6,0X20);
         writeADV7619Reg(0X6C,0XD7,0X20);
         writeADV7619Reg(0X6C,0XD8,0X00);
         writeADV7619Reg(0X6C,0XD9,0X00);
         writeADV7619Reg(0X6C,0XDA,0X00);
         writeADV7619Reg(0X6C,0XDB,0XFF);
         writeADV7619Reg(0X6C,0XDC,0X00);
         writeADV7619Reg(0X6C,0XDD,0X0A);
         writeADV7619Reg(0X6C,0XDE,0X20);
         writeADV7619Reg(0X6C,0XDF,0X20);
         writeADV7619Reg(0X6C,0XE0,0X20);
         writeADV7619Reg(0X6C,0XE1,0X20);
         writeADV7619Reg(0X6C,0XE2,0X20);
         writeADV7619Reg(0X6C,0XE3,0X20);
         writeADV7619Reg(0X6C,0XE4,0X20);
         writeADV7619Reg(0X6C,0XE5,0X20);
         writeADV7619Reg(0X6C,0XE6,0X20);
         writeADV7619Reg(0X6C,0XE7,0X20);
         writeADV7619Reg(0X6C,0XE8,0X20);
         writeADV7619Reg(0X6C,0XE9,0X20);
         writeADV7619Reg(0X6C,0XEA,0X00);
         writeADV7619Reg(0X6C,0XEB,0X00);
         writeADV7619Reg(0X6C,0XEC,0X00);
         writeADV7619Reg(0X6C,0XED,0X00);
         writeADV7619Reg(0X6C,0XEE,0X00);
         writeADV7619Reg(0X6C,0XEF,0X00);
         writeADV7619Reg(0X6C,0XF0,0X00);
         writeADV7619Reg(0X6C,0XF1,0X00);
         writeADV7619Reg(0X6C,0XF2,0X00);
         writeADV7619Reg(0X6C,0XF3,0X00);
         writeADV7619Reg(0X6C,0XF4,0X00);
         writeADV7619Reg(0X6C,0XF5,0X00);
         writeADV7619Reg(0X6C,0XF6,0X00);
         writeADV7619Reg(0X6C,0XF7,0X00);
         writeADV7619Reg(0X6C,0XF8,0X00);
         writeADV7619Reg(0X6C,0XF9,0X00);
         writeADV7619Reg(0X6C,0XFA,0X00);
         writeADV7619Reg(0X6C,0XFB,0X00);
         writeADV7619Reg(0X6C,0XFC,0X00);
         writeADV7619Reg(0X6C,0XFD,0X00);
         writeADV7619Reg(0X6C,0XFE,0X00);
         writeADV7619Reg(0X6C,0XFF,0XDA);
         writeADV7619Reg(0X64,0X77,0X00); //Set the Most Significant Bit of the SPA location to 0
         writeADV7619Reg(0X64,0X52,0X20); //Set the SPA for port B.
         writeADV7619Reg(0X64,0X53,0X00); //Set the SPA for port B.
         writeADV7619Reg(0X64,0X70,0X9E); //Set the Least Significant Byte of the SPA location
         writeADV7619Reg(0X64,0X74,0X03); //Enable the Internal EDID for Ports
        


         writeADV7619Reg(0x68, 0xC0, 0x02);//0x03 //ADI Required Write
         writeADV7619Reg(0x98, 0x01, 0x06); //Prim_Mode =110b HDMI-GR
         writeADV7619Reg(0x98, 0x02, 0xF5); //F7 //Auto CSC, 0xRGB, 0xSet op_656 bit
         writeADV7619Reg(0x98, 0x03, 0x82); //24 bit SDR 422 Mode 0
         writeADV7619Reg(0x98, 0x05, 0x28); //AV Codes Off
         writeADV7619Reg(0x98, 0x06, 0xA0); //No inversion on VS,HS pins
         writeADV7619Reg(0x98, 0x0C, 0x42); //Power up part
         writeADV7619Reg(0x98, 0x15, 0x80); //Disable Tristate of Pins
         writeADV7619Reg(0x98, 0x19, 0x83); //LLC DLL phase
         writeADV7619Reg(0x98, 0x33, 0x40); //LLC DLL MUX enable
         writeADV7619Reg(0x44, 0xBA, 0x01); //Set HDMI FreeRun
         writeADV7619Reg(0x44, 0x6C, 0x00); //Required ADI write
         writeADV7619Reg(0x64, 0x40, 0x81); //Disable HDCP 1.1 features
         writeADV7619Reg(0x4C, 0xB5, 0x01); //Setting MCLK to 256Fs
         writeADV7619Reg(0x68, 0xC0, 0x03); //ADI Required write
         writeADV7619Reg(0x68, 0x00, 0x08); //Set HDMI Input Port A (BG_MEAS_PORT_SEL = 001b)
         writeADV7619Reg(0x68, 0x02, 0x03); //ALL BG Ports enabled
         writeADV7619Reg(0x68, 0x03, 0x98); //ADI Required Write
         writeADV7619Reg(0x68, 0x10, 0xA5); //ADI Required Write
         writeADV7619Reg(0x68, 0x1B, 0x08); //ADI Required Write
         writeADV7619Reg(0x68, 0x45, 0x04); //ADI Required Write
         writeADV7619Reg(0x68, 0x97, 0xC0); //ADI Required Write
         writeADV7619Reg(0x68, 0x3D, 0x10); //ADI Required Write
         writeADV7619Reg(0x68, 0x3E, 0x69); //ADI Required Write
         writeADV7619Reg(0x68, 0x3F, 0x46); //ADI Required Write
         writeADV7619Reg(0x68, 0x4E, 0xFE); //ADI Required Write
         writeADV7619Reg(0x68, 0x4F, 0x08); //ADI Required Write
         writeADV7619Reg(0x68, 0x50, 0x00); //ADI Required Write
         writeADV7619Reg(0x68, 0x57, 0xA3); //ADI Required Write
         writeADV7619Reg(0x68, 0x58, 0x07); //ADI Required Write
         writeADV7619Reg(0x68, 0x6F, 0x08); //ADI Required Write
         writeADV7619Reg(0x68, 0x83, 0xFC); //Enable clock terminators for port A & B
         writeADV7619Reg(0x68, 0x84, 0x03); //ADI Required Write
         writeADV7619Reg(0x68, 0x85, 0x10); //0x11 //ADI Required Write
         writeADV7619Reg(0x68, 0x86, 0x9B); //ADI Required Write
         writeADV7619Reg(0x68, 0x89, 0x03); //ADI Required Write
         writeADV7619Reg(0x68, 0x9B, 0x03); //ADI Required Write
         writeADV7619Reg(0x68, 0x93, 0x03); //ADI Required Write
         writeADV7619Reg(0x68, 0x5A, 0x80); //ADI Required Write
         writeADV7619Reg(0x68, 0x9C, 0x80); //ADI Required Write
         writeADV7619Reg(0x68, 0x9C, 0xC0); //ADI Required Write
         writeADV7619Reg(0x68, 0x9C, 0x00); //ADI Required Write
         writeADV7619Reg(0x72, 0x01, 0x00); //Set N Value(6144)
         writeADV7619Reg(0x72, 0x02, 0x18); //Set N Value(6144)
         writeADV7619Reg(0x72, 0x03, 0x00); //Set N Value(6144)
         writeADV7619Reg(0x72, 0x15, 0x01); //24bit Input 422 (YCrCb) with Separate Syncs, 0x44.1kHz fs
         writeADV7619Reg(0x72, 0x16, 0x61); //YCrCb 444
         writeADV7619Reg(0x72, 0x18, 0x46); //CSC disabled
         writeADV7619Reg(0x72, 0x3B, 0x80); //PR Auto Mode
         writeADV7619Reg(0x72, 0x40, 0x80); //General Control Packet Enable
         writeADV7619Reg(0x72, 0x41, 0x10); //Power Down control
         writeADV7619Reg(0x72, 0x48, 0x08); //Data right justified
         writeADV7619Reg(0x72, 0x49, 0xA8); //Set Dither_mode - 12-to-10 bit
         writeADV7619Reg(0x72, 0x4C, 0x04); //8 bit Output
         writeADV7619Reg(0x72, 0x55, 0x20); //0x00 //Set RGB 444 in AVinfo Frame
         writeADV7619Reg(0x72, 0x56, 0x08); //Set active format Aspect
         writeADV7619Reg(0x72, 0x96, 0x20); //HPD Interrupt clear
         writeADV7619Reg(0x72, 0x98, 0x03); //ADI Required Write
         writeADV7619Reg(0x72, 0x99, 0x02); //ADI Required Write
         writeADV7619Reg(0x72, 0x9C, 0x30); //PLL Filter R1 Value
         writeADV7619Reg(0x72, 0x9D, 0x61); //Set clock divide
         writeADV7619Reg(0x72, 0xA2, 0xA4); //ADI Required Write
         writeADV7619Reg(0x72, 0xA3, 0xA4); //ADI Required Write
         writeADV7619Reg(0x72, 0xAF, 0x16); //Set HDMI Mode
         writeADV7619Reg(0x72, 0xBA, 0x60); //No clock delay
         writeADV7619Reg(0x72, 0xDE, 0x9C); //ADI Required Write
         writeADV7619Reg(0x72, 0xE4, 0x60); //VCO Swing Reference Voltage
         writeADV7619Reg(0x72, 0xFA, 0x7D); //Nbr of times to search for good phase
        

        /* Enable EDID for PC HDMI output */
         writeADV7619Reg(0x64, 0x74, 0x3); //EDID_A_ENABLE, Addr 64 (Repeater), Address 0x74[0](port A) Address 0x74[1] (portB)
        

        sleep(1);
        

        //Toggle HPA line to force PC to reload EDID
         writeADV7619Reg(0x68, 0x6C, 0x1);
         writeADV7619Reg(0x98, 0x20, 0x88);
         writeADV7619Reg(0x98, 0x20, 0x8);
        

        //set HPS high
         writeADV7619Reg(0x98, 0x20, 0x88);
        

        return 0;
        }
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        •  Super User  
        
            
						
                            
            
            				
            
                on Aug 30, 2023 3:13 AM
            
            
												
						in reply to CharlieT
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hi,
        

          I can only find the edid data for adv7611, I assume the adv7619 is using the similar edid data ?
        

              Yes, Both part can use the similar edid data.
        

          Please ensure with below things,
        

          This issue seems the EDID has not been sent to the PC source.  
        

          As per specification, the low to high HPD transition should cause the Source to read the EDID.
        

          At first, We need to load the EDID data into the ADV7619, then toggle the HPD low then high. The HPD low to high should force the source to read the EDID data from the 7619.
        

          Another way is
             Load the EDID into the ADV7619 and then we need plug in the HDMI cable. This will give a low to high transition after the internal EDID has been programmed.
        

          As stated, Sometimes PC has failed to get the correct EDID, So toggle the HPA line to force the PC to re-read the EDID (Follow below sequence) and then check whether you could able to read the 256 bytes.
        1) ADV7619 HDMI 0x68 0x6C[0] = 1, HPA_MAN_VALUE_X
        2) ADV7619 IO 0x98 0x20[3] = 0, HPA_A pin active
        3) ADV7619 IO 0x98 0x20[7] = 0, HPA_MAN_VALUE_A, sets HPA low
        4) load up the EDID
        5) ADV7619 IO 0x98 0x20[7] = 1, HPA_MAN_VALUE_A, sets HPS high, forces source to reload EDID
        

        So do
        0x68 0x6C=0xA1
        0x98 0x20=0x30
        load new EDID info
        0x98 0x20=0xF0, set HPA high, forcing source to read EDID.
        Forcing the source to reload the EDID data.
        

        SPA - Source Physical Address:
                   This is part of the CEA block in the EDID memory. Basically, it sets up CEC addressing which needs to change for each RX port.
           Source to Port A will read the EDID as-is.
           The source to Port B will read the EDID data and as the EDID data is read, the byte stream will be modified on the fly at the SPA_LOCATION with the values defined in       SPA_PORT_B. The block checksum will be updated also on the fly.
        SPA is just 2 bytes, Assume SPA_A = 0000 hex, then SPA_B might be 0001 hex
        

           Note that, When the EDID is read by the source, the ADV7619 will update the SPA value depending on which port is reading it on the fly.
        

        Here expert gave some suggestion about how to load EDID (+) How can I use ADV7611 with an internal EDID - Q&A - Video - EngineerZone (analog.com)
        

        Please note that, If this configuration doesn't help, then we need to check it on your hardware side w.r.t 'DDC & HPD' lines.
        

        

        Thanks,
        

        Poornima
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
						
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	
      



Reply

        


      • 
	
        



	
			
		
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
        •  Analog Employees  
        •  Super User  
        
            
						
                            
            
            				
            
                on Aug 30, 2023 3:13 AM
            
            
												
						in reply to CharlieT
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hi,
        

          I can only find the edid data for adv7611, I assume the adv7619 is using the similar edid data ?
        

              Yes, Both part can use the similar edid data.
        

          Please ensure with below things,
        

          This issue seems the EDID has not been sent to the PC source.  
        

          As per specification, the low to high HPD transition should cause the Source to read the EDID.
        

          At first, We need to load the EDID data into the ADV7619, then toggle the HPD low then high. The HPD low to high should force the source to read the EDID data from the 7619.
        

          Another way is
             Load the EDID into the ADV7619 and then we need plug in the HDMI cable. This will give a low to high transition after the internal EDID has been programmed.
        

          As stated, Sometimes PC has failed to get the correct EDID, So toggle the HPA line to force the PC to re-read the EDID (Follow below sequence) and then check whether you could able to read the 256 bytes.
        1) ADV7619 HDMI 0x68 0x6C[0] = 1, HPA_MAN_VALUE_X
        2) ADV7619 IO 0x98 0x20[3] = 0, HPA_A pin active
        3) ADV7619 IO 0x98 0x20[7] = 0, HPA_MAN_VALUE_A, sets HPA low
        4) load up the EDID
        5) ADV7619 IO 0x98 0x20[7] = 1, HPA_MAN_VALUE_A, sets HPS high, forces source to reload EDID
        

        So do
        0x68 0x6C=0xA1
        0x98 0x20=0x30
        load new EDID info
        0x98 0x20=0xF0, set HPA high, forcing source to read EDID.
        Forcing the source to reload the EDID data.
        

        SPA - Source Physical Address:
                   This is part of the CEA block in the EDID memory. Basically, it sets up CEC addressing which needs to change for each RX port.
           Source to Port A will read the EDID as-is.
           The source to Port B will read the EDID data and as the EDID data is read, the byte stream will be modified on the fly at the SPA_LOCATION with the values defined in       SPA_PORT_B. The block checksum will be updated also on the fly.
        SPA is just 2 bytes, Assume SPA_A = 0000 hex, then SPA_B might be 0001 hex
        

           Note that, When the EDID is read by the source, the ADV7619 will update the SPA value depending on which port is reading it on the fly.
        

        Here expert gave some suggestion about how to load EDID (+) How can I use ADV7611 with an internal EDID - Q&A - Video - EngineerZone (analog.com)
        

        Please note that, If this configuration doesn't help, then we need to check it on your hardware side w.r.t 'DDC & HPD' lines.
        

        

        Thanks,
        

        Poornima
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
						
						
				
				
		
		
        
			
		
        
	
        

        

        • 


      


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