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CSC Function on ADV7610

Category: Datasheet/Specs
Product Number: ADV7610

Hello,

I've received questions for CEC of ADV7610. Could you check following query?

Item 1 : Regarding CSC from YPbPr IN to YPbPr OUT

They're using following register settings. If they'd like to make the configuration of "YPbPr IN to YPbPr OUT", can it be achieved by simply changing "address 0x02 -> 0xF2" to "address 0x02 -> 0xF0"?

If it needs any other settings, please let me know.

Item 2 : Regarding 24bit SDR422 mode

Their current setting is 24bit SDR 422 mode. With the current settings for "YPbPr in + YPbPr out", is the 12 pin for Y output/PbPr output 0 padding for the lower 4 bits?

If this is used as "RGB in + YPbPr out" and internal CSC is used, will the internal calculation result come out in 12bit full? Or is the lower 4 bits 0 padding (if 0 padding, I would like to know whether it is rounded or truncated)?

Best Regards,

S.O.

  • Hi,

      Please find the below comments,

    1. Kindly let us know, Are you converting from RGB color space to YPbPr OUT then the register setting from "address 0x02 -> 0xF2" to "address 0x02 -> 0xF0" rare correct and also crosscheck your configuration with reference one some of the recommended settings are missing.

    2. Regarding 24bit SDR422 mode, Please refer Pixel pin assignment and there we can find the details of how the pixel port pins are assigned for YPbPr output of 24bit SDR422 Mode and also we came to know the pins that need to be not connected.

     

    Thanks,

    Poornima

  • Item 1 : following settings are all of the registers they use currently. As you commented "some of the recommended settings are missing", does it still have any missing? Please add the registers in below list if there're any required register.

    CID   Offset   initialize stop 480i/576i 480p/576p others    
    1  ADV7611_IO 0x4C  ADV7611_IO_REG_FF 0xFF  0x80  0x80  0x80  0x80  //Main reset
     wait 5ms  wait 5ms  wait 5ms
    2  ADV7611_IO 0x4C  ADV7611_SELECT_HDMI_SLAVE_ADDRESS 0xFB  0x68  0x68  0x68  0x68  //HDMI
    3  ADV7611_IO 0x4C  ADV7611_SELECT_CP_SLAVE_ADDRESS 0xFD  0x44  0x44  0x44  0x44  //CP
    4  ADV7611_IO 0x4C  ADV7611_SELECT_DPLL_SLAVE_ADDRESS 0xF8  0x4C  0x4C  0x4C  0x4C  //DPLL Map
    5  ADV7611_IO 0x4C  ADV7611_IO_REG_14 0x14  0x55  0x55  0x55  //Drivability settings for HDMI output
    6  ADV7611_IO 0x4C  ADV7611_IO_REG_15 0x15  0x80  0x80  0x80  0x80  0x80  //Disable Tristate of Pins
    7  ADV7611_IO 0x4C  ADV7611_IO_REG_0C 0x0C  0x62  0x42  0x42  0x42  //ADI recommended setting
    8  ADV7611_IO 0x4C  ADV7611_PRIMARY_MODE 0x01  0x06  0x06  0x06  //Prim_Mode =110b HDMI-GR
    9  ADV7611_IO 0x4C  ADV7611_IO_REG_02 0x02  0xF2/F0  0xF2/F0  0xF2/F0  //Auto CSC & RGB out
    10  ADV7611_IO 0x4C  ADV7611_IO_REG_03 0x03  0x8A  0x8A  0x8A  //16 bit SDR 422(0x80)⇒24bit SDR ITU-656 422 Mode2(0x8A)
    11  ADV7611_IO 0x4C  ADV7611_IO_REG_05 0x05  0x28  0x28  0x28  //AV Codes Off
    12  ADV7611_IO 0x4C  ADV7611_IO_REG_0B 0x0B  0x47  0x47  0x44  0x44  0x44  //ADI recommended setting
    13  ADV7611_IO 0x4C  ADV7611_IO_REG_BF 0xBF  0x01  0x01  0x01  //Bypass CP core
    14  ADV7611_CP 0x4C  ADV7611_SYNC_CNTRL_1 0x7C  0x00  0x00  0x00  //Do not invert HS and VS polarity
    15  ADV7611_CP 0x4C  ADV7611_HDMI_CP_CNTRL_1 0xBA  0x01  0x01  0x01  //Set HDMI Free Run
    16  ADV7611_DPLL_MAP 0x26  ADV7611_DPLL_REG_C3 0xC3  0xC0  0xC0  0x80  //ADI recommended setting
    17  ADV7611_HDMI 0x34  ADV7611_HDMI_REGISTER_1B 0x1B  0x00  0x00  0x00  //Cause Deep Colour FIFO to ignore DPLL Locked Status
    18  ADV7611_HDMI 0x34  ADV7611_HDMI_REGISTER_0_0H 0x00  0x08  0x08  0x08  //ADI recommended setting
    19  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_6E 0x6E  0x50  0x50  0x50  //MUX_LeftJustify
    20  ADV7611_HDMI 0x34  ADV7611_MUTE_CTRL 0x1A  0x82  0x82  0x82  //Unmute audio
    21  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_44 0x44  0x05  0x05  0x05  //ADI recommended setting
    22  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_CE 0xCE  0x24  0x24  0x24  //ADI recommended setting
    23  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_57 0x57  0xB9  0xB9  0xB9  //ADI recommended setting
    24  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_58 0x58  0x63  0x63  0x63  //ADI recommended setting
    25  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_72 0x72  0xD4  0xD4  0xD4  //Lowest DDC drive strength and slew rate
    26  ADV7611_HDMI 0x34  ADV7611_DDC_PAD 0x73  0x01  0x01  0x01  0x01  //Disable DDC Pads
    27  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_75 0x75  0x10  0x10  0x10  //ADI recommended setting
    28  ADV7611_HDMI 0x34  ADV7611_HDMI_REGISTER_0_2H 0x83  0xFE  0xFE  0xFE  //ADI recommended setting
    29  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_84 0x84  0x00  0x00  0x00  //ADI recommended setting
    30  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_98 0x98  0xFF  0xFF  0xFF  //HDMI ADI recommended write
    31  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_99 0x99  0xA1  0xA1  0xA1  //HDMI ADI recommended write
    32  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_9A 0x9A  0xFF  0xFF  0xFF  //HDMI ADI recommended write
    33  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_9B 0x9B  0x09  0x09  0x09  //HDMI ADI recommended write
    34  ADV7611_HDMI 0x34  ADV7611_HDMI_REG_8E 0x8E  0xAA  0xAA  0xAA  //Bypass Equaliser
    35  ADV7611_IO 0x4C  ADV7611_IO_REG_06 0x06  0xA6  0xA6  //Toggling Vsync and Hsync polarities ( INV_VS_POL & INV_HS_POL )
    36  ADV7611_HDMI 0x34  ADV7611_REGISTER_41H 0x41  0x50  //Enable manual PR setting : PR factor is 1
    37  ADV7611_IO 0x4C  ADV7611_IO_REG_41 0x41  0x31  0x31  0x31  //MCLK=OFF

    Item 2 : The customer is prepareing the additional comments. Please wait for the updates.

  • Adding my comments for the details of Item 2. Could you clarify following each question?

    [ Case of "YPbPr input YPbPr output" ]

    As for the red letter part in below image, lower 4 bit may be 0 padding on both Y PbPr, Is it correct?

    [ Case of "RGB input YPbPr output" ]

    As for the red letter part in below image, In the CSC calculation is the bit accuracy inside far more than12bit? And is output bit width is it rounded or truncated to 8bit according to the input 8bit? or fully 12bit output for keeping calculation bit accuracy?

    Please also keep comment for Item1

  • Hi,

      Please let us know, why we need to go for lower 4 bit zero Padding/Truncating Since ADV7610 have an option to support 24 bit output mode ?

       If we have the respective output bit support, then why should we Rounding / Truncating the output bits.

    Thanks,

    Poornima

  • Hi,

    This is a question of CSC calculation accuracy, not for pin assignment. As I mentioned above, they're using 24bit SDR 422 mode for the pin assign. Since the format is 422, they're asking for the CSC calculation spec when it working in each case such as Rounding / Truncating with the outputs of lower bits. It's needed for defining the customer product specification.

    Please let us know the answer for Item1 and 2.

  • Hi,

     We don't have any CSC calculation spec other than what provided in the manuals so we need to check with expert about how Rounding / Truncating can affect the CSC calculation.

     CSC calculation been little elaborately provided in ADV7401 Manual. Please refer section 6.5.1 of the ADV7403 Datasheet Manual (ADV7403_Manual_RevB.pdf) that provides more details about CSC coefficient calculation, which is available at ADV7403 Design Support Files.

     Also Please refer this thread understanding ADV7513 CSC behavior - Q&A - Video - EngineerZone (analog.com)

    Thanks,

    Poornima

  • Hi,

    I understand the comments for item2. How about the question of Item1? Do you have any comments whether it's enough with the uploaded list?

    Item 1 : following settings are all of the registers they use currently. As you commented "some of the recommended settings are missing", does it still have any missing? Please add the registers in below list if there're any required register.

  • Hi,

     Regarding Item 1,  We have script for YPrPb input to YPrPb output So Please follow our exact script register configuration.

     Difference from reference one been highlighted in yellow color.

    Please note that, If those ADI Recommended writes are not included, the part would not work reliably (unless those values are default anyway).Those registers are generally internal settings that let us handle process variation which is why they are determined during characterization. The settings that show up as "ADI Recommended Settings" are the values that work reliably across voltage and temperature.

    Thanks,

    Poornima

  • Sorry for jumping in, I also have similar questions on ADV7610, and I have several following questions.

    Item3 

    There are 2 points for CSC function, CP and Backend ColorSpace.


    There are many settings for CP part CSC, but I can't find setting for Backend ColorSpace Conversion part.
    Is there a setting for Backend ColorSpace Conversion part?

    And also I'd like to know detail function on Backend ColorSpace.
    What is the purpose of this Backend ColorSpace conversion and why it is located here?

    Item4 (similar to Item1)

    As for the "ADI recommended" setting,

    I found the same setting on ADV7611, and there are comment of
    "for non-fast switching application".

    What is this "non-fast switching" ? A frequent format change?
    I can't link this "for non-fast switching application" to what your mentioned
    "the values that work reliably across voltage and temperature". Is the situation of ADV7610 different from that of ADV7611?

    And also I'd like to know the "risk" that these "ADI recommended settings" are not set.
    What is the risk to be considered?

    Item5

    As for the IO address 0x02h, the setting of 0xF5h means the Auto CSC and YPbPr out as the output of CP block.
    This "Auto CSC" means that checking the input AVI info and by the combination of input color space detected by the AVI info
    and RGB_OUT setting, color space conversion is determined, is it correct?

    If so by this 0x98h, 0x02h 0xF5h setting both HDMI YPbPr input and RGB input can be converted YPbPr output as ADV7610 colorspace output automatically, am I right?

    Item6

    I use the setting of IO map address 0xBF and set 0x01, it means bypass CP core.

    If this setting is done and if the "24bit SDR ITU-656 422 Mode2 " is chosen as the output assignment

    and if HDMI input is RGB, what would happen?

  • Hi Katsuya San,

            Please find the below comments,

    What is the purpose of this Backend ColoSpace conversion and why it is located here?

        "Back End CSC" is nothing, but the CSC in the CP and it is not an extra one.

         The use of the CP CSC prevents timing mismatches between the luma and the chroma channels that can occur when the DPP CSC is used.
         Also, ADV7610 automatically configures the DPP CSC depending on the input and output formats and the use of the color control feature and note that DPP CSC is always in pass-through mode unless the ADV7610 is processing an RGB input, outputting this input in the RGB color space and VID_ADJ_EN is enabled. 
    ADI Recommended Setting:
         These are register values which are determined during characterization and values are given that you must write. They sometimes change from recommended settings version to version. They are not documented, you simply need to write the value as per recommended setting / Script.

    Please note that, If those writes are not included, Part would not expect to work reliably .

    Those registers are generally internal settings that let us handle process variation which is why they are determined during characterization. The settings that show up as "ADI Recommended Settings" are the values that work reliably across different voltage and temperature. They really should be called "ADI Required settings".
    Non-Fast Switching Mode:
       Fast switching is nothing but the part can lock to an video source more quickly in less than 1 second between two HDMI ports.
        This feature allows the user of a system containing the chip to seamlessly switch between HDCP encrypted sources. There is no delay in achieving video output which was previously caused by HDCP authentication. The time required to switch between HDMI sources with HDCP encryption is reduced to a fraction of a second.

    As for the IO address 0x02h, the setting of 0xF5h means the Auto CSC and YPbPr out as the output of CP block.
    This "Auto CSC" means that checking the input AVI info and by the combination of input color space detected by the AVI info
    and RGB_OUT setting, color space conversion is determined, is it correct?
       In automatic CSC mode, the user is required to program the input color space and the output color space for the correct operation of the
    CSC matrix.
          Manual CSC mode allows the user to program all the color space conversion by manually programming CSC coefficients.
    Note:
      ADV761x output is RGB, then you should use CP_MODE_GAIN_ADJ to increase brightness.
      ADV761x output is YCbCr/YPbPr, then you should use BRIGHTNESS_CNTRL to increase brightness.

    98 02 F5 ; Auto CSC, YCrCb Out, Set op_656 bit
    98 02 F7 ; Auto CSC, RGB Out, Set op_656 bit
    I use the setting of IO map address 0xBF and set 0x01, it means bypass CP core. ?
       
        Bypassing the CP means we can't do any color space conversion or other manipulation of the video data.
        Please note that, For full processing of the HDMI input, the CP core needs to be powered up.
        Also On this part, the STDI block is located within the CP core, bypassing the CP core is not a valid thing to do if you are using the STDI block.
    Thanks,
    Poornima