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ADV7393: DC Offset on Output of DAC1

AkiJupic

on Apr 24, 2023

Category: Hardware

Product Number: ADV7393

Hello,

We are using ADV7393 to output an NTSC video signal on its DAC output pin DAC1 (pin 28). The chip is being used in low-drive operation with a 300 Ohm load.

An offset of 40mV-50mV (with respect to GND) was observed on the output video signal. The offset is observed even when the output is decoupled from the rest of the circuitry (while still leaving the 300 Ohm load). The same DC offset is observed on the output when the video signal is turned off/disabled.

I'll ask questions that were asked in a similar thread for the ADV7341 chip (linked here: RE: DC Offset on ADV7341 video output).

1) Is there a way to remove or minimize this offset with either a register setting or a passive component change?

2) What is causing this offset? Is this an inherent characteristic of the chip?

Our video image quality is good, however, this offset is causing us to fail one of our requirements. We are looking for a solution that does not require additional circuitry (e.g., AC coupling into a buffer to remove the offset).

Regards,

Aki

Tags: Video Products hardware adv7393 Video Encoders dc offset adv7341 Show More

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0 PoornimaSubramani

over 1 year ago
Hi,

As per expert comment, Other than AC coupling to remove Offset instead We can use series capacitors to completely block the DC current flow through the signal path (The Cap is a DC blocking cap).

The series capacitors block this DC offset and the input pin will bias the signal that is acceptable to the part.

Also we can remove DC-Offset with a high-pass filter.

Please note that, a slight offset on the DAC output will not have any effect in video quality since downstream sink can adjust to account for this offset.

Thanks,

Poornima
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0 PoornimaSubramani

over 1 year ago
Hi,

As per expert comment, Other than AC coupling to remove Offset instead We can use series capacitors to completely block the DC current flow through the signal path (The Cap is a DC blocking cap).

The series capacitors block this DC offset and the input pin will bias the signal that is acceptable to the part.

Also we can remove DC-Offset with a high-pass filter.

Please note that, a slight offset on the DAC output will not have any effect in video quality since downstream sink can adjust to account for this offset.

Thanks,

Poornima
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0 AkiJupic
over 1 year ago in reply to PoornimaSubramani
Hi Poornima,

AC coupling implies using series DC-blocking capacitors (though all capacitors are DC-blocking, so that's redundant to state).

As I have mentioned in my original post, we are looking for a solution that does not require additional circuitry so a high pass filter would not suffice.

I do agree that the slight offset doesn't effect our image, but it does make us fail a design requirement.

Can you confirm that this offset is an inherent characteristic of the device and that the offset cannot be minimized/removed with a register setting or a passive component addition/modification?

Thanks,

Aki
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0 FormerMember

over 1 year ago in reply to AkiJupic

Almost all video decoders AC couple their inputs. That way even video that is offset by several volts will work correctly. Normally video doesn't care about a bit of offset.

The ADV7393 has a current DAC output where the sync level is defined as the lowest level in the waveform. In this case the DAC, even when set to 0 bits, still has some output current. There is no direct register control to change the offset around however you might try changing the Gain control (0x0B) to see if this forces sync level lower so it passes your test. Of course you'll need to retest the new waveform to make sure it meets all your requirements. I have not tried this, it would be interesting if this worked.

If you look closely at SMPTE 170, the NTSC spec does not define voltage levels but rather it defines the waveform in IRE ratios where Figure B.1 only references IRE to voltage with a total IRE range of -40 to 100 equaling a voltage range of -0.286 to 0.714 volts. There is no specification that the Sync level be exactly 0V. This is what your offset fix is trying to do.

If you absolutely need the sync pulse to be at 0V then you could pull the load resistor to -40mV instead of ground. This would bias the entire waveform by 40mV down.

My initial thought about this thread is that one of your requirements doesn't meet SMPTE 170 specs.

Let me know if you have more questions.

0 AkiJupic

over 1 year ago in reply to FormerMember

Hi Guenter,

First of all, the detailed reply is very much appreciated.

Yes, I agree: almost all video decoders AC couple their inputs. However, we are interfacing with a custom video decoder and we are DC coupled to it via an FDA, i.e., the ADV7393 DAC output is fed into a FDA and then transmitted as a balanced 75 Ohm signal. After the FDA, that offset turns into ~80mV to ~100mV.

The Sync level requirement on the custom video decoder side is 0V, hence where that specification comes from. Otherwise if it was a regular decoder, we'd be completely fine with the offset.

I'll try varying the Gain control of the encoder to see if that works. Thank you for the suggestion.

Unfortunately, I can't play with the reference on the load resistor side. That's set in stone.

If the Gain control doesn't do the trick, I'll look into adding an offset into the inverting input of the FDA.

Thanks,

Aki