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ADV7610 - Dark horizontal lines

Hello,

 

As you can see in the picture attached, some dark horizontal lines appear on video as soon as I move a window on the edge of the screen.

What could be the cause? What is the parameter that could fix it? Is it something related to color, contrast or brightness?

Below you can also find the ADV7610 configuration used.

 

Thank you in advance for your support.

 

    // IO Map
    0x980xFF0x80, // I2C reset
    0x980xF40x80, // Programmable I2C slave address for CEC map
    0x980xF50x7C, // Programmable I2C slave address for Infoframe map
    0x980xF80x4C, // Programmable I2C slave address for DPLL map (careful since only apparently same IO Map address)
    0x980xF90x64, // Programmable I2C slave address for KSV map
    0x980xFA0x6C, // Programmable I2C slave address for EDID map
    0x980xFB0x68, // Programmable I2C slave address for HDMI map
    0x980xFD0x44, // Programmable I2C slave address for CP map
    0x980x010x06, // Vertical frequency 60Hz, primary mode HDMI-GR (graphics)
    0x980x020xF2, // Auto CSC mode, no conversion, full 0 to 255 output range, RGB color space output, data saturator disabled
    0x980x030x40, // Data format and pixel bus configuration: 24-bit SDR 4:4:4 mode
    0x980x040x62, // Default pixel pins configuration (P[23:16] R, P[15:8] G, P[7:0] B) and XTAL frequency selection (28.63636 MHz)
    0x980x050x28, // DE output selected, blank data during blanking periods, AV codes off
    0x980x060xA2, // VSYNC output selected, negative DE polarity, negative VSYNC polarity, positive HSYNC polarity, do not invert LLC
    0x980x0B0x44, // Power up CP, digital sections of HDMI block, and XTAL buffer to the digital core
    0x980x0C0x42, // Chip is operational, power save mode disabled, powers up CP core clock, and digital output pins pads
    0x980x140x7F, // Set max drive strength for output data, LLC, HSYNC, VSYNC, and DE
    0x980x150x80, // Disable tristate of pins
    // CP Map
    0x440x910x00, // Progressive video mode
    0x440xBA0x00, // Disable HDMI free run
    0x440xC90x2D, // Disable buffering of timing parameters used for free run in HDMI mode
    0x440xF20x04, // Enable CRC checking
    // KSV (Repeater) Map
    0x640x400x81, // Disable HDCP 1.1 features
    // HDMI Map
    0x680x000x00, // I2C address for HDCP port is 0x74, set HDMI input Port A
    0x680x830xFE, // Enable clock termination on port A
    0x680x8D0x04, // LF gain equalizer settings
    0x680x8E0x1E, // HF gain equalizer settings
    0x680x1A0x8A, // Discard audio sample packets with invalid parity bit, unmute audio
    0x680x960x01, // Enable HDMI Equalizer Dynamic Control
    0x680x9B0x03, // ADI recommended setting
    0x680x6F0x08, // ADI recommended setting
    0x680x850x1F, // ADI recommended setting
    0x680x870x70, // ADI recommended setting
    0x680x570xDA, // ADI recommended setting
    0x680x580x01, // ADI recommended setting
    0x680xC10x01, // ADI recommended setting
    0x680xC20x01, // ADI recommended setting
    0x680xC30x01, // ADI recommended setting
    0x680xC40x01, // ADI recommended setting
    0x680xC50x01, // ADI recommended setting
    0x680xC60x01, // ADI recommended setting
    0x680xC70x01, // ADI recommended setting
    0x680xC80x01, // ADI recommended setting
    0x680xC90x01, // ADI recommended setting
    0x680xCA0x01, // ADI recommended setting
    0x680xCB0x01, // ADI recommended setting
    0x680xCC0x01, // ADI recommended setting
    0x680x750x10, // DDC drive strength
Parents
  • Hi,

     Below register configurations seems different from reference one. Please configure accordingly and let us know after that,

         // 0x98, 0x02, 0xF2 98 02 F5  Auto CSC, RGB out, Set op_656 bit

         // 0x98, 0x06, 0xA2 98 06 A6 ; Invert VS, HS pins

         // 0x44, 0xBA, 0x00 44 BA 01 ; Set HDMI FreeRun

     According to reference script 0x06 register is configured as A6 (i.e Positive polarity Hs/Vs/Field).But in your configuration it seems as negative polarity(98 06 A2).

     Please note that, by changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of the downstream devices processing the output data of the ADV7610. It is expected that these parameters must be matched regardless of the type of video data that is transmitted. Therefore, INV_LLC_POL is designed to be mode independent.

    Thanks,

    Poornima

  • Hi Poornima,

    Thanks for your fast reply.

    We modified register 0x02 of the IO map taking into consideration the reference value as below:

    0x980x020xF7, // Auto CSC mode, no conversion, limited 16 to 235 output range, RGB color space output, data saturator disabled

    We cannot set the register value exactly to 0xF5 because the downstream video pipeline does not operate in YPbPr color space but in RGB.

    However, even after modifying the content of this register, the dark band issue was not solved.

    Concerning the two other registers you pointed out, we did not modify them because of the following reasons:

    • We use a negative polarity VSYNC to match with the downstream video pipeline (developed on FPGA). That is why we write 0xA2 instead of 0xA6 in register 0x06 of the IO map.
    • We do not want the HDMI free run mode to be enabled as the input signal is properly controlled and we do not want a video stream to be injected when no data is at the input. 

    Do you have any other idea on how to solve this dark horizontal line issue? I indeed believe it is something related to color, contrast, brightness...

    Thanks,

    Mattia

  • Hi,

    Please crosscheck with your source whether RGB limited or Full range is coming from the source.

    Register - 0x53(Readback of the HDMI input color space decoded from several fields in the AVI Info Frame) which is available to check whether RGB limited or full range coming from the source So accordingly set the input source to either RGB Limited Range or RGB Full Range input mode .

    Full range sets the RGB levels (0-255): So set the input source to RGB full range and then the IO map 0x02, would be 0xF2.
    Limited range sets the RGB levels (16-235): So set the input source to RGB limited range and IO map, 0x02 would be 0xF6.

    Please note that,HDMI color space which is decoded from AVI Infoframe. The input range is set by control register INP_COLOR_SPACE and the read back register HDMI_COLORSPACE[3:0] ,The output color space is determined the control bit OP_656_RANGE.

    Also by configuring the OP_656_RANGE between 0 & 1, We can increase or decrease the brightness.
    For example: By setting "OP_656_RANGE to 0" and the display appears full brightness and to reduce the brightness, Set "OP_656_RANGE to 1".
    Kindly note, If the HDMI receiver is configured for RGB output, Use CP_MODE_GAIN_ADJ to increase brightness (Affects all the three channels simultaneously)
    If the HDMI receiver is configured for YCbCr output, BRIGHTNESS_CNTRL to increase brightness (affects only the luma channel).

    Thanks,

    Poornima

  • Hello,

    we finally managed to solve this horizontal lines issue (for a reminder check the video in attachment).

    The problem was caused by the digital fine clamp block present inside the CP. From page 103 of the Hardware User Guide (Rev.0) we understood that:

    "The incoming video signal level is measured at the back porch. The level error, that is, clamp error, is compensated for by subtracting or adding a digital number."

    This explains why what we saw on the video was looking like a filter applied to the whole line as soon as we had something touching/crossing the left edge of the frame (first pixel of each line).

    To solve the issue we set to '1' the value of the CLMP_FREEZE field in register 0x6C[5] in the CP block (address 0x44). Observe that this register is not documented in the Software Manual (Rev.0). 

    Kind regards,

    Mattia

Reply
  • Hello,

    we finally managed to solve this horizontal lines issue (for a reminder check the video in attachment).

    The problem was caused by the digital fine clamp block present inside the CP. From page 103 of the Hardware User Guide (Rev.0) we understood that:

    "The incoming video signal level is measured at the back porch. The level error, that is, clamp error, is compensated for by subtracting or adding a digital number."

    This explains why what we saw on the video was looking like a filter applied to the whole line as soon as we had something touching/crossing the left edge of the frame (first pixel of each line).

    To solve the issue we set to '1' the value of the CLMP_FREEZE field in register 0x6C[5] in the CP block (address 0x44). Observe that this register is not documented in the Software Manual (Rev.0). 

    Kind regards,

    Mattia

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